High performance Pch-LDMOS transistors in wide range voltage from 35V to 200V SOI LDMOS platform technology

Shimamoto, Satoshi; Yanagida, Yohei; Shirakawa, Shingo; Miyakoshi, Kazuo; Imai, Tetsuo; Oshima, Takayuki; Sakano, J.; Wada, S.

doi:10.1109/ispsd.2011.5890786

Cited by 14 publications

(3 citation statements)

References 3 publications

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“…[68] Hence, the structure is limited to 120 V for which an R SP of about 2.2 Ω mm 2 is achieved for a LOCOS drift length of about 9 μm. Other SOI PLDMOS configurations are reported that use multiple field plates [84,85] and deep-trench field plates [86,87].…”

Section: (B) Soi Pldmosmentioning

confidence: 99%

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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This chapter focuses mainly on the drain-extended MOS transistor, DEMOS, for high voltage applications, and on the lateral double-diffused MOS transistor, LDMOS, for high power applications. In both cases, the drain is extended with a lightly-doped region, referred to as the drift region, to sustain the high voltage. The chapter begins with an analysis of the drift region and its optimization, typically by reduced surface-field (RESURF) techniques. The transistor switching performance is then analyzed, followed by a discussion of DEMOS and LDMOS design considerations and characteristics. High-voltage and high-current effects are then described, including quasi-saturation, body current, on-state breakdown, and safe operating area (SOA). The chapter concludes with selected high-voltage device applications. IntroductionThe MOSFETs discussed in Chap. 6 are designed for digital, analog, mixed-signal, and RF applications that operate in the low-to-medium voltage range of about 0.8-6 V. Many analog applications, however, require transistors that can handle voltages above 20 V and currents in the ampere range. Those transistors are referred to as high-voltage and power transistors. This chapter provides a comprehensive analysis of the drain-extended MOS transistor (DEMOS), for high-voltage and low-current applications, and the lateral double-diffused MOS (LDMOS) transistor, LDMOS, for power applications. (The "D" in LDMOS describes the sequential (double) diffusion of boron and arsenic through the same oxide opening, defining a precise channel length (Chap. 9). The "L" means that the current path is parallel to the silicon surface (lateral), as opposed to "V" in VDMOS where the current is nearly vertical to the silicon surface.) Schematic cross sections of both transistors (Table 7.1). The DEMOS is typically processed without added process complexity, whereas the LDMOS requires optimization of the P-body and N-drift regions to achieve high voltages and currents while minimizing the drain-to-source resistance and transistor area.The interest in bipolar, CMOS, and DMOS (BCD) technologies has been driven primarily by the proliferation of portable electronics, automotive electronics, and the need for energy efficiency. These applications cluster around different operating points, with 24 V for portable electronics; 60 V for automotive, solar, and LED backlighting; 85 V for power over Ethernet; 120 V for telecommunication; and 700 V for offline LED lighting, consumer, and industrial applications. As a result, BCD is now the technology of choice to realize power ICs by most integrated device manufacturers (IDM) and foundries [1][2][3][4][5].This chapter focuses mainly on transistors with voltage capabilities in the range of 20-700 V, where the bulk of the product applications lie.

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Section: (B) Soi Pldmosmentioning

confidence: 99%

High-Voltage and Power Transistors

El-Kareh¹,

Hutter²

2015

Silicon Analog Components

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“…With the increase of demand for more complex and faster logic function in analog power IC, it is significant to improve the performance of the lateral double-diffused metal-oxide-semiconductor transistor (LDMOS), specially minimizing specific on-resistance (R on,sp ) and maximizing off-state breakdown voltage (BV) [1][2][3][4][5][6][7][8][9]. Most developed technologies focus on the drift region optimizing to improve the trade-off of R on,sp vs. BV for LDMOS devices [10][11][12][13][14][15][16][17][18][19][20].…”

Section: Introductionmentioning

confidence: 99%

Ultra-Low Specific On-resistance Lateral Double-Diffused Metal-Oxide-Semiconductor Transistor with Enhanced Dual-Gate and Partial P-buried Layer

et al. 2019

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An ultra-low specific on-resistance (Ron,sp) lateral double-diffused metal-oxide-semiconductor transistor (LDMOS) with enhanced dual-gate and partial P-buried layer is proposed and investigated in this paper. On-resistance analytical model for the proposed LDMOS is built to provide an in-depth insight into the relationship between the drift region resistance and the channel region resistance. N-buried layer is introduced under P-well to provide a low-resistance conduction path and reduce the resistance of the channel region significantly. Enhanced dual-gate structure is formed by N-buried layer while avoiding the vertical punch-through breakdown in off-state. Partial P-buried layer with optimized length is adopted under the N-drift region to extend vertical depletion region and relax the electric field peak in off-state, which enhances breakdown voltage (BV) with low drift region resistance. For the LDMOS with enhanced dual-gate and partial P-buried layer, the result shows that Ron,sp is 8.5 mΩ·mm2 while BV is 43 V.

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“…The p-channel lateral double-diffused MOSFET (LDMOS) fabricated in silicon-on-insulator (SOI) has been widely used as a high-side power switch [1]- [3]. However, under the same requirement of breakdown voltage (BV), a p-LDMOS usually has a larger specific on-resistance (R on,sp ) than an n-LDMOS.…”

Section: Introductionmentioning

confidence: 99%

A Novel p-LDMOS Additionally Conducting Electrons by Control ICs

Guo

Chen

2019

IEEE J. Electron Devices Soc.

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A silicon-on-insulator (SOI) p-channel lateral double-diffused MOSFET (p-LDMOS), conducting not only holes but also electrons, is proposed and investigated by TCAD simulations. Its most important advantage is the greatly improved relationship between the breakdown voltage (BV) and the specific on-resistance (R on,sp ). The improvement is mainly attributed to two aspects. First, many holes can accumulate in the p-drift region in the on-state, which provides a low-resistance path for hole conduction. Second, a paralleled n-LDMOS is, meanwhile, automatically triggered to form a new path for electrons. Electrons have higher mobility than holes; thus, the device performance is further improved. Based on a simulation comparison with the previous p-LDMOS at the same BV of 300 V, the R on,sp of the proposed p-LDMOS decreased by 78% and the figure of merit (FOM) increased approximately 3.4 times. Moreover, the proposed device still has the conventional three-terminal style, and its fabrication process is compatible with CMOS technology.INDEX TERMS High-side switch, power MOSFET, silicon-on-insulator.

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High performance Pch-LDMOS transistors in wide range voltage from 35V to 200V SOI LDMOS platform technology

Cited by 14 publications

References 3 publications

High-Voltage and Power Transistors

High-Voltage and Power Transistors

Ultra-Low Specific On-resistance Lateral Double-Diffused Metal-Oxide-Semiconductor Transistor with Enhanced Dual-Gate and Partial P-buried Layer

A Novel p-LDMOS Additionally Conducting Electrons by Control ICs

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