High‐Performance Partially Printed Hybrid CMOS Inverters Based on Indium‐Zinc‐Oxide and Chirality Enriched Carbon Nanotube Thin‐Film Transistors

Abstract

Inkjet printing is a promising technique to fabricate thin-film transistors (TFTs) and integrated complementary metal-oxidesemiconductor (CMOS) circuits because of its patterned Complementary metal-oxide-semiconductor (CMOS) inverters with low power consumption and high noise immunity are essential for realizing practical applications of printed logic gates and circuits. However, the performance of existing printed CMOS inverters is still unsatisfactory because p-type and n-type transistors do not match well. This work demonstrates novel low-voltage and high-performance CMOS inverters using partially printed thin-film transistors (TFTs) on 50 nm HfO 2 /Si substrates based on n-type indium zinc oxides (IZOs) and p-type chirality enriched (9,8) semiconducting single-walled carbon nanotubes (SWCNTs). The high-k dielectric materials grown using atomic layer deposition and (9,8) SWCNTs with relatively large band gaps help to match the characteristics of p-type and n-type transistors-the IZO and SWCNT TFTs exhibit similar mobility on/off ratio, small hysteresis, and low sub-threshold swing at low operating voltages. The hybrid CMOS inverters demonstrate excellent performance with the highest voltage gain up to 45, the largest noise margin of 83% at 1/2 V dd , and the lowest static power consumption of 0.4 µW at V dd of 2 V among recently reported printed CMOS inverters under relatively low annealing temperatures (300 °C). The strategies demonstrated here can be considered as general approaches to realize a new generation of high-performance printed logic gates and circuits. Printable ElectronicsThe ORCID identification number(s) for the author(s) of this article can be found under https://doi.

Hybrid Thin-Film Materials Combinations for Complementary Integration Circuit Implementation

“…Further, the strong localization of the valence band maximum (VBM) to oxygen ions leads to a large hole effective mass and low mobility [77][78][79]. For this reason, most metal oxide semiconductors are an n-type material, and even p-type metal oxide semiconductors such as CuO, SnO, and NiO show poor charge mobility [80]. Moreover, because most of the low-temperature deposition techniques of metal oxide The voltage transfer characteristics of a hybrid CMOS inverter under supply voltages of 1 V to 5 V. The dashed curve shows power consumption at 1 V (adapted from [63] with permission from John Wiley and Sons).…”

“…Further, the strong localization of the valence band maximum (VBM) to oxygen ions leads to a large hole effective mass and low mobility [77][78][79]. For this reason, most metal oxide semiconductors are an n-type material, and even p-type metal oxide semiconductors such as CuO, SnO, and NiO show poor charge mobility [80]. Moreover, because most of the low-temperature deposition techniques of metal oxide semiconductors have mainly considered n-type materials (for example, indium oxide (In 2 O 3 ), indium zinc oxide (IZO), and IGZO), efforts to implement p-type metal oxide devices on flexible substrates are still lacking [81,82].…”

“…Moreover, because most of the low-temperature deposition techniques of metal oxide semiconductors have mainly considered n-type materials (for example, indium oxide (In 2 O 3 ), indium zinc oxide (IZO), and IGZO), efforts to implement p-type metal oxide devices on flexible substrates are still lacking [81,82]. In 2019, Luo et al implemented a low-voltage, highperformance complementary inverter with an n-channel IZO TFT and a p-channel chiralityenriched (9,8) semiconducting single-walled carbon nanotube (SWCNT) FET using a partial printing method [80]. Inkjet printing is a highly fascinating process for fabricating TFTs or integrating CMOS circuits because of customizability based on patterned deposition and a simple patterning process for a large-scale array.…”

“…Figure 2. (a) Top view OM image of an IGZO TFT fabricated with an inkjet printing method (adapted from[80] with permission from John Wiley and Sons). (b) Output voltage characteristics of a 3D CMOS inverter allowing a bending radius up to 2.6 mm (adapted from[83] with permission from John Wiley and Sons).…”

SINTESIS LAPISAN TIPIS TiO2:(F+In) PADA SUBSTRAT KACA DENGAN METODE SPIN-COATING SEBAGAI BAHAN SEL SURYA

“…Lapisan tipis merupakan salah satu bentuk pengembangan yang dihasilkan dari adanya kemajuan teknologi dalam kehidupan manusia. Lapisan ini dapat berupa senyawa organik ataupun anorganik yang sifatnya semikonduktor (Luo, et al 2019). Lapisan tipis biasa dibuat dengan mendeposisikan suatu senyawa di atas suatu media yang disebut substrat (Abegunde, et al 2019).…”