High-performance packet classification on GPU

Zhou, Shijie; Singapura, Shreyas G.; Prasanna, Viktor K.

doi:10.1109/hpec.2014.7041005

Cited by 23 publications

(14 citation statements)

References 18 publications

(21 reference statements)

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“…The GPU implementation delivers an average throughput of 10.7 and 4.8 Mpps with rule number of 500 and 2k, respectively. Zhou et al [34] propose a GPU implementation of a range-tree search and a decomposition-based bit vector (BV) tree approach. The algorithm scales well across a range of rules-set sizes from 512 to 4k rules and demonstrates a throughput improvement factor of 1.9 compared with the implementation of another multi-core platform.…”

Section: A Related Workmentioning

confidence: 99%

“…Hardware-based algorithms are used to accelerate existing classification algorithms using different hardware platforms such as FPGAs [7], [10], [11], [32], multiple-core CPUs [8], and GPUs [22]. Some packet classification algorithms have been implemented using GPU to maintain line speed [22], [33], [34]. Varvello et al [22] demonstrate GPU-accelerated versions for three classification search algorithms: linear search, tuple search, and bloom filters search.…”

Section: Introductionmentioning

confidence: 99%

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Packet Classification Using GPU and One-Level Entropy-Based Hashing

et al. 2020

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The demand for on-line analyzing of internet traffic for both security and QoS consideration directly increases as a function of using diverse applications and as malicious attacks increase. This paper presents a new fast parallel packet classification algorithm based on entropy hashing. The algorithm uses a one-level hashing data structure and enables partitioning a very large rules-set into smaller uniformly distributed sub-rules look-up tables based on maximum entropy and Most Significant Bit (MSB) pattern hash keys. This minimizes the classifier searches only to the relevant appropriate look-up table using the same hash key, and therefore significantly shortens the classification process. A further speed-up factor is achieved by parallelizing the classification algorithm using Nvidia Graphics Processing Unit (GPU). The proposed algorithm is applied to both ACL and FW applications using common synthetic rules-sets of size up to 500k rules. The simulation results show that the proposed algorithm outperforms existing classifiers in terms of both speed up and memory utilization. The required memory size is significantly reduced, and a classification speed-up factor of up to 200 is demonstrated compared to a similar serial approach.

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Section: A Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Packet Classification Using GPU and One-Level Entropy-Based Hashing

et al. 2020

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“…The presence of this simulator satisfies the need for real and heterogeneous filters of Firewalls, IP-Chains, and Access Control Lists. In the majority of the studies [44][45][46][47][48], the ClassBench tool has been used for producing the required data structure due to a need for filters and packets that are close to reality in terms of structural characteristics and statistical distribution.…”

Section: Rule Set Generation Tools and Evaluation Parametersmentioning

confidence: 99%

Ingredients to enhance the performance of two-stage TCAM-based packet classifiers in internet of things: greedy layering, bit auctioning and range encoding

Abbasi

Vakilian

Fanian

et al. 2019

J Wireless Com Network

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Using packet classification algorithms in network equipment increases packet processing speed in Internet of Things (IoT). In the hardware implementation of these algorithms, ternary content-addressable memories (TCAMs) are often preferred to other implementations. As a common approach, TCAMs are used for the parallel search to match packet header information with the rules of the classifier. In two-stage architectures of hardware-based packet classifiers, first the decision tree is created, and then the rules are distributed among its leaves. In the second step, depending on the corresponding leaves, the second part of the rules, which includes the range of source and destination ports is stored in different blocks of TCAM. Due to inappropriate storage of port range fields, the existing architectures face the problem of wasting memory and growing power consumption. This paper proposes an efficient algorithm to encode the port range. This algorithm consists of three general steps including layering, bit allocation, and encoding. A greedy algorithm in the first step places the ranges with higher weights in higher layers. Next, an auction-based algorithm allocates several bits to each layer depending on the number of the ranges in that layer. Finally, in each layer, depending on the weight order of the ranges, the bits are given values for the intended range. The evaluation results show that unlike previous methods of storing range fields, the proposed method not only increases the speed of the classification but also uses the capacity of TCAM in the second stage more efficiently.

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“…More specifically, a group of studies has focused on accelerating the packet classification [91] on GPUs. Zhou et al [92] have proposed a two-phase algorithm. In the first phase, each thread examines a set of rules and produces a local classification result, using a binary range-tree search technique.…”

Section: Related Workmentioning

confidence: 99%

System-Level Design of GPU-Based Embedded Systems

Maghazeh

2018

Linköping Studies in Science and Technology. Dissertations

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Modern embedded systems deploy several hardware accelerators, in a heterogeneous manner, to deliver high-performance computing. Among such devices, graphics processing units (GPUs) have earned a prominent position by virtue of their immense computing power. However, a system design that relies on the sheer throughput of GPUs is often incapable of satisfying the strict power-and time-related constraints faced by the embedded systems. This thesis presents several system-level software techniques to optimize the design of GPU-based embedded systems under various graphics and nongraphics applications. As compared to the conventional application-level optimizations, the system-wide view of our proposed techniques brings about several advantages: First, it allows for fully incorporating the limitations and requirements of the various system parts in the design process. Second, it can unveil optimization opportunities by exposing the information flow between the processing components. Third, the techniques are generally applicable to a wide range of applications with similar characteristics. In addition, multiple system-level techniques can be combined together or with the applicationlevel techniques to further improve performance. We begin by studying some of the unique attributes of GPU-based embedded systems and discussing several factors that distinguish the design of these systems from that of the conventional high-end GPU-based systems. We then proceed to develop two techniques that address an important challenge in the design of GPU-based embedded systems, from two different perspectives. The challenge arises from the fact that GPUs require a large amount of workload to be present at runtime in order to deliver a high throughput. However, for some embedded applications, collecting large batches of input data requires an unacceptable waiting time, prompting a trade-off between throughput and latency. We also develop an optimization technique for GPU-based applications to address the memory bottleneck issue by utilizing the GPU L2 cache to shorten data access time. Moreover, in the area of graphics applications, with a focus on mobile games, we propose a power management scheme to reduce the GPU power consumption by dynamically adjusting the display resolution while considering the user's visual perception at various resolutions. We also discuss the collective impact of the proposed techniques in tackling the design challenges of the emerging complex systems. The proposed techniques are assessed by real-life experimentations on GPU-based hardware platforms, which demonstrate the superior performance of our approaches as compared to the state-of-the-art techniques. The research presented in this thesis has been partially funded by the National Computer Science Graduate School (cugs) in Sweden. v First and foremost, I would like to thank Professor Zebo Peng, Professor Petru Eles, and Dr. Unmesh Bordoloi for their excellent support and thoughtful supervision of my Ph.D. studies and for their patience and understanding...

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High-performance packet classification on GPU

Cited by 23 publications

References 18 publications

Packet Classification Using GPU and One-Level Entropy-Based Hashing

Packet Classification Using GPU and One-Level Entropy-Based Hashing

Ingredients to enhance the performance of two-stage TCAM-based packet classifiers in internet of things: greedy layering, bit auctioning and range encoding

System-Level Design of GPU-Based Embedded Systems

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