High performance on-chip differential signaling using passive compensation for global communication

Zhang, Bo; Tsuchiya,; Hashimoto, Masanori; Kuh,; Cheng, Wood-Hi

doi:10.1109/aspdac.2009.4796511

Cited by 12 publications

(5 citation statements)

References 12 publications

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“…The latency of sub-network activation/deactivation consists of the following components: delay in the H-tree network, delay in the central controller, delay from the central controller to laser, and the laser operation delay. Assuming a 3cm × 3cm multi-processor chip, the H-tree differential T-line delay in 22nm is estimated as 8.04 ps/mm [22]. So the H-tree transmission delay is estimated to be 240 ps.…”

Section: The Architecture Supportmentioning

confidence: 99%

ESPN: A case for energy-star photonic on-chip network

2013

International Symposium on Low Power Electronics and Design (ISLPED)

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Photonic Network-on-Chips (NoCs) have recently been proposed due to their inherent low latency and high bandwidth. However, the high static power of the photonic components (e.g. laser source, resonators and waveguides) often results in energyinefficient architectures. In this paper, we advocate the EnergyStar Photonic Network (ESPN) architecture that optimizes energy utilization via a two-pronged approach: (1) by enabling dynamic resource provisioning, ESPN adapts photonic network resources based on runtime traffic characteristics and (2) by utilizing all-optical adaptive routing, ESPN improves energy efficiency by intelligently exploiting existing network resources without introducing high latency and power hungry auxiliary routing mechanisms. Our evaluation results show that compared to the baseline design, ESPN reduces power and energy consumption under synthetic traffic patterns by 50% and 58% respectively.

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Section: The Architecture Supportmentioning

confidence: 99%

ESPN: A case for energy-star photonic on-chip network

2013

International Symposium on Low Power Electronics and Design (ISLPED)

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“…[149] Chip-to-Chip Ultra Path [150], [151] IFIS [33], [152]- [154] PCIe [155] CXL [156], [157] Cache Coh. (CCIX) [158] Gen-Z [159] OpenCAPI [160], [161] ? Capacity & Access BW [179] Memory Store Cube [180] Proc.…”

Section: ) Instruction Set Acceleration (Isacc)mentioning

confidence: 99%

“…In addition to cache coherency, OpenCAPI supports direct memory access, atomic operations to host memory, messages across devices, and interrupts to the host platform. High frequency differential signaling technology [161] is employed to achieve high bandwidth and low latency connections between hardware accelerators and CPU. The address translation and coherency cache access constructs are encapsulated by OpenCAPI through serialization which is implemented on the platform hardware (e.g., CPU socket) to minimize the latency and computation overhead on the accelerator device.…”

Section: F: Generation-z (Gen-z)mentioning

confidence: 99%

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

2020

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In order to facilitate flexible network service virtualization and migration, network functions (NFs) are increasingly executed by software modules as so-called "softwarized NFs" on General-Purpose Computing (GPC) platforms and infrastructures. GPC platforms are not specifically designed to efficiently execute NFs with their typically intense Input/Output (I/O) demands. Recently, numerous hardwarebased accelerations have been developed to augment GPC platforms and infrastructures, e.g., the central processing unit (CPU) and memory, to efficiently execute NFs. This article comprehensively surveys hardware-accelerated platforms and infrastructures for executing softwarized NFs. This survey covers both commercial products, which we consider to be enabling technologies, as well as relevant research studies. We have organized the survey into the main categories of enabling technologies and research studies on hardware accelerations for the CPU, the memory, and the interconnects (e.g., between CPU and memory), as well as custom and dedicated hardware accelerators (that are embedded on the platforms); furthermore, we survey hardware-accelerated infrastructures that connect GPC platforms to networks (e.g., smart network interface cards). We find that the CPU hardware accelerations have mainly focused on extended instruction sets and CPU clock adjustments, as well as cache coherency. Hardware accelerated interconnects have been developed for on-chip and chip-to-chip connections. Our comprehensive up-to-date survey identifies the main trade-offs and limitations of the existing hardware-accelerated platforms and infrastructures for NFs and outlines directions for future research.

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“…Consequently, the RC dominated on-chip interconnects have become a major bottleneck in the realization of systems on a chip using scaled-down technologies. 1,2 Some unidirectional signaling schemes have been presented to obtain higher data-rates with better energy-efficiency across on-chip global interconnects [3][4][5][6] by utilizing different techniques such as data modulation, resistively and capacitively driven solutions, and current-mode signaling. [7][8][9][10][11][12][13][14][15][16] Besides, some half-duplex signaling solutions have been presented in the literature.…”

Section: Introductionmentioning

confidence: 99%

A full‐duplex transceiver for 20‐Gbps high‐speed simultaneous bidirectional signaling across global on‐chip interconnections

Jarihani

Sturm

Tonello

2021

Circuit Theory & Apps

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This paper presents a high‐speed simultaneous bidirectional transceiver (SBT) for on‐chip wireline communications. A MOS hybrid transistor is utilized to split the received data from the superimposed signal at both ends of the on‐chip interconnection with the assistance of two drivers, namely main and auxiliary. Moreover, a high‐pass filter (HPF) is used as a differentiator to generate the echo cancelation signal. Consequently, the echo‐cancelation for simultaneous bidirectional signaling (SBS) is realized by the combination of the hybrid device and the differentiator. The proposed SBT has been designed and evaluated using 28‐nm CMOS technology over a narrow 5‐mm on‐chip interconnection, which possesses 11.9‐dB loss at the Nyquist frequency (half a bit rate). The energy‐efficiency of the proposed full‐duplex transceiver (FDT) for 20‐Gbps simultaneous bidirectional data transmission is 0.147 PJ/b/mm. The performance results show that the proposed SBT has better overall performance compared to the previous architectures reported in the literature to date. The layout of the presented SBT occupies a low area of 1574 μm2.

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High performance on-chip differential signaling using passive compensation for global communication

Cited by 12 publications

References 12 publications

ESPN: A case for energy-star photonic on-chip network

ESPN: A case for energy-star photonic on-chip network

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

A full‐duplex transceiver for 20‐Gbps high‐speed simultaneous bidirectional signaling across global on‐chip interconnections

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