2018
DOI: 10.1109/led.2018.2825645
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High-Performance Normally-OFF GaN MIS-HEMTs Using Hybrid Ferroelectric Charge Trap Gate Stack (FEG-HEMT) for Power Device Applications

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Cited by 39 publications
(15 citation statements)
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“…by increasing the threshold voltage or the ON/OFF ratio) of such transistors. [1][2][3] However the integration of such ferroelectric materials (usually perovskites [2,[4][5][6][7] ) on GaN is challenging due to the large lattice mismatch between the two structures and a buffer layer, such as MgO, [2,7] Al2O3, [6] or TiO2, [8] is commonly used to allow for the mismatch. Direct integration of a fully epitaxial ferroelectric material on GaN is the promise of further improvement for such devices.…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation
“…by increasing the threshold voltage or the ON/OFF ratio) of such transistors. [1][2][3] However the integration of such ferroelectric materials (usually perovskites [2,[4][5][6][7] ) on GaN is challenging due to the large lattice mismatch between the two structures and a buffer layer, such as MgO, [2,7] Al2O3, [6] or TiO2, [8] is commonly used to allow for the mismatch. Direct integration of a fully epitaxial ferroelectric material on GaN is the promise of further improvement for such devices.…”
Section: Introductionmentioning
confidence: 99%
“…[20][21][22] ALD however always results in polycrystalline films, with an overall polarization smaller compared to the polarization of single grains, in addition to the need of a wake-up process. Other techniques such as sputtering, [23] MOCVD [24] (including on GaN [1] ) or CSD [25] have been explored, similarly resulting in polycrystalline films. On the contrary, Pulsed Laser Deposition (PLD) is a vapor phase technique that allows the direct epitaxial growth of thin films.…”
Section: Introductionmentioning
confidence: 99%
“…In the GaN HEMT power device structure, the 2DEG (with respect to the piezoelectric and spontaneous polarization of the GaN) [11] forms without any gate voltage, which confirms that the GaN devices are naturally depletion-mode (D-mode) or normally-on. Further, the fabrication of enhancement-mode or normally-off (E-mode) GaN HEMT power devices is implemented by several methods: the combination of a metal-insulator-semiconductor (MIS) stack with the use of gate recess [12]; the integration of a series connection between the normally-on GaN HEMT and low-voltage Si Metal Oxide Semiconductor Field Effect Transistor (MOSFET) cascode package [13,14]; the fluorine implantation [15]; the oxide charge engineering [16]; and the use of a p-AlGaN [17] or p-GaN as p-type gate material [18], where the conduction band shifts towards up, and results a depletion for the channel of negative gate voltages. Among D-mode and E-mode GaN HEMTs, the E-mode device is preferred for most PEAs as it requires to evince a normally-off condition with large power range [19].…”
Section: Introductionmentioning
confidence: 99%
“…Generally, the trapping effect in an MIS gate stack could be related to the traps at/near the interface, named interface states/border traps, or in the bulk of the insulator [ 9 ]. There have been several techniques used to suppress threshold voltage shift to date, including pre-fluorination argon treatment [ 10 ], sputter-deposited Al O [ 11 ], in-situ pre-deposition plasma nitridation [ 12 ], metal-organic chemical vapor deposition-grown in situ SiN [ 13 , 14 ], hybrid ferroelectric charge trap gate stack [ 15 ], etc., to reduce the trapping effect at/near the insulator/semiconductor interface. Due to the low deposition temperature, there also exists large density of traps in the bulk of the gate insulators deposited by PECVD or ALD.…”
Section: Introductionmentioning
confidence: 99%