High Performance Low-Voltage Power MOSFETs with Hybrid Waffle Layout Structure in a 0.25μ Standard CMOS Process

Yoo, Abraham; Chang, Michael; Trescases, Olivier; Ng, Wai Tung

doi:10.1109/ispsd.2008.4538906

Cited by 21 publications

(13 citation statements)

References 2 publications

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“…This is then connected to higher level of metal by contacts and vias up to the top metal level. Figure 3.9 depicts the typical multi-fingers connection of the transistor array which not only reduces the gate resistance but it also reduces the junction capacitances [90,91].…”

Section: Power Transistor Layoutmentioning

confidence: 99%

Design of power management circuits for fully on-ship applications

Tan¹

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With the fast growing electronic portable devices, power management becomes an important area in electronic industry to reduce the power consumption so as to extend the battery life of these devices. Low dropout (LDO) regulator is widely used in power management IC due to its simple structure, low noise and fast speed characteristics. As the technology continues scaling down to deep submicron, the digital circuits display less immunity to Process, Supply voltage, and Temperature (PVT) variations.

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Section: Power Transistor Layoutmentioning

confidence: 99%

Design of power management circuits for fully on-ship applications

Tan¹

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“…The waffle layout structure is occupied by the inter-connection of metal rather than the active area which result in the turn on resistance of the power MOS to be reduced to a greater extent. Thus, for the same size of power MOS, waffle structure layout will yield a much smaller turn on resistance as compared to multi-figure layout [97]. However, the area occupied by waffle layout is much larger than the multi-finger structure and it requires special PDK to support which may not be practical in normal process.…”

Section: Layout Design Of Power Mosmentioning

confidence: 99%

“…Its presence can be explained due to the fact that power PMOS and NMOS has different current characteristic. If the offset voltage in the valley current sensing output is97 removed, the accuracy of the valley current sensing can yield > 97% accuracy for a load ranging from 25 to 535 mA.…”

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confidence: 99%

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Adaptive efficiency optimized power regulator for portable devices

Wu¹

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An adaptive efficiency optimized power regulator that can work at load current ranging from mille-ampere to ampere is developed for portable devices. Based on the proposed efficiency tracking method, the power regulator can adjust its efficiency to the highest as the load current or supply voltage varies. An internal 10-µA, trim-free, low temperature coefficient, supply independent current reference with process compensation feature is proposed to ensure that the system remains stable over PVT variations. Without using high gain

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“…However, a larger power transistor size consumes a larger silicon area and increases the gate driving losses which contributes to higher switching power losses. Hence, different layout techniques are discussed in [133][134][135] [136].…”

Section: Power Losses and Efficiencymentioning

confidence: 99%

Low power AC-DC converters for wireless power transfer application

Low¹

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First of all, I would like to express my deepest and sincere gratitude to my supervisor, Dr. Siek Liter for his priceless guidance and encouragement throughout my studies. Dr. Siek is inspirational, knowledgeable, understanding, helpful, cheerful, etc. He has all the traits of a great professor. I truly appreciate his patience and continuous guidance which help to cultivate my analytical thinking skills as well as problem solving skills. I am deeply thankful for his encouragement especially during the most difficult time of my PhD journey. Next, I would like to thank EDB and my sponsored company, Maxim Integrated for funding my studies and providing me a short training. I would also like to thank NTU-A*STAR Silicon Technologies Centre of Excellence, School of Electrical and Electronic (EEE) for supporting the chip fabrication and also VIRTUS for providing me a conducive research environment. Besides, I would also like to thank my seniors, Sun ZhuoChao and Roy Chew Kin Wai for sharing their knowledge and experiences with me, which helps to widen my perspectives on the research areas. My gratitude is also extended to my fellow teammates and friends

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High Performance Low-Voltage Power MOSFETs with Hybrid Waffle Layout Structure in a 0.25μ Standard CMOS Process

Cited by 21 publications

References 2 publications

Design of power management circuits for fully on-ship applications

Design of power management circuits for fully on-ship applications

Adaptive efficiency optimized power regulator for portable devices

Low power AC-DC converters for wireless power transfer application

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