2013
DOI: 10.1021/am404490t
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High-Performance Low-Cost Back-Channel-Etch Amorphous Gallium–Indium–Zinc Oxide Thin-Film Transistors by Curing and Passivation of the Damaged Back Channel

Abstract: High-performance, low-cost amorphous gallium-indium-zinc oxide (a-GIZO) thin-film-transistor (TFT) technology is required for the next generation of active-matrix organic light-emitting diodes. A back-channel-etch structure is the most appropriate device structure for high-performance, low-cost a-GIZO TFT technology. However, channel damage due to source/drain etching and passivation-layer deposition has been a critical issue. To solve this problem, the present work focuses on overall back-channel processes, s… Show more

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Cited by 36 publications
(27 citation statements)
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References 38 publications
(61 reference statements)
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“…9 For these reasons the bias stress stability of IGZO-TFTs has been intensely investigated where effects of composition, process temperature, process conditions, gate dielectric, back channel passivation, and many other factors have been evaluated. [10][11][12][13][14][15] Proposed mechanisms for bias stress threshold voltage (V th ) shifts include electron trapping at the semiconductor/dielectric interface, electron injection into the dielectric, or formation of sub-band gap states in the bulk of films. It has also been suggested that adsorbed species (e.g., O 2 and H 2 O) on the back channel of the IGZO-TFTs can be the dominant mechanism for device instability, by providing acceptor or donor states or through field induced adsorption or desorption of these species.…”
mentioning
confidence: 99%
“…9 For these reasons the bias stress stability of IGZO-TFTs has been intensely investigated where effects of composition, process temperature, process conditions, gate dielectric, back channel passivation, and many other factors have been evaluated. [10][11][12][13][14][15] Proposed mechanisms for bias stress threshold voltage (V th ) shifts include electron trapping at the semiconductor/dielectric interface, electron injection into the dielectric, or formation of sub-band gap states in the bulk of films. It has also been suggested that adsorbed species (e.g., O 2 and H 2 O) on the back channel of the IGZO-TFTs can be the dominant mechanism for device instability, by providing acceptor or donor states or through field induced adsorption or desorption of these species.…”
mentioning
confidence: 99%
“…Therefore, the N 2 O treated device exhibited a high mobility of 37.0 cm 2 Vs −1 , low SS of 0.25 V/ decade and low I off of 10 −13 A ( figure 12(b)). The switching property and BTS induced stability of dry etching-based BCE IGZO TFTs can be improved further by optimizing the N 2 O plasma treatment, deposition conditions and post annealing of the SiO 2 passivation layer [79].…”
Section: Bce Architecture For Low Fabrication Costmentioning
confidence: 99%
“…Furthermore, the overlapped regions between ESL and S-D make the channel length difficult to be less than 5 μm. Until now, several back-channel-etched (BCE) methods have been reported to fabricate a-IGZO TFT [6][7][8][9][10]. These methods can be classified into 3 categories.…”
Section: Introductionmentioning
confidence: 99%
“…These methods can be classified into 3 categories. The first one to pattern the S-D electrodes is using dry etching with post N 2 O plasma treatment [6]. Although the device performance could be recovered after post treatment on the back channel, the stability is always deteriorated.…”
Section: Introductionmentioning
confidence: 99%