High-performance InSb based quantum well field effect transistors for low-power dissipation applications

Ashley, T.; Emeny, M. T.; Hayes, D.G.; Hilton, K.P.; Jefferies, Richard; Maclean, J.O.; Smith, Stuart; Tang, A.; Wallis, D. J.; Webber, P. J.

doi:10.1109/iedm.2009.5424207

Cited by 12 publications

(13 citation statements)

References 5 publications

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“…[1][2][3][4][5][6][7][8][9][10][11][12] High performance III-V MOSFETs require low source and drain (S/D) series resistance R S/D , which includes metal-semiconductor contact resistance. [13][14][15][16][17][18] To achieve low R S/D in III-V FETs, S/D engineering such as selective growth of in situ doped S/D materials [19][20][21] and self-aligned contacts have been employed.…”

mentioning

confidence: 99%

Reduction of Off-State Leakage Current in In0.7Ga0.3As Channel n-MOSFETs with Self-Aligned Ni-InGaAs Contact Metallization

Zhang

Guo

Lin

et al. 2011

Electrochem. Solid-State Lett.

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In 0.7 Ga 0.3 As channel n-MOSFETs (metal-oxide-semiconductor field-effect transistors) with Si-doped S/D and self-aligned NiInGaAs contact were demonstrated for the first time. The salicide-like metallization process employed a direct reaction between Ni and Si-doped InGaAs, followed by the removal of the unreacted Ni. As compared with n-MOSFETs with metallic Ni-InGaAs S/D (i.e. no Si doping in S/D), n-MOSFETs with Ni-InGaAs contact formed on Si-doped S/D show significantly improved OFFstate current I OFF in the linear and saturation regions.III-V materials such as Indium Gallium Arsenide (InGaAs) and Indium Arsenide (InAs) have significantly higher electron mobility than Silicon (Si) and are attractive for future high speed low power logic applications. 1-12 High performance III-V MOSFETs require low source and drain (S/D) series resistance R S/D , which includes metal-semiconductor contact resistance. 13-18 To achieve low R S/D in III-V FETs, S/D engineering such as selective growth of in situ doped S/D materials 19-21 and self-aligned contacts have been employed. [17][18]21,22 Metallic S/D is another attractive option 23-26 and should preferably be self-aligned to the gate stack. InGaAs channel n-MOSFETs with self-aligned metallic Ni-InGaAs S/D have been demonstrated recently. 25,26 However, the n-MOSFETs with metallic S/D suffer from high leakage current at metal/semiconductor junctions in S/D regions, leading to high drain to source and drain to body leakage current. Low drain junction leakage is needed to achieve low standby power consumption.In this work, In 0.7 Ga 0.3 As channel n-MOSFETs with Si-doped S/ D and self-aligned Ni-InGaAs contact were demonstrated for the first time. The spacer-less metallization process is similar to salicidation and drives the diffusion of Ni into InGaAs for reaction to form a conductive material. S/D implant (Si) and dopant activation anneal were performed before the metallization to form n-InGaAs/ p-InGaAs junction. The n-MOSFETs with Si-doped S/D and NiInGaAs contact show significantly suppressed off-state current I OFF as compared with n-MOSFETs with metallic Ni-InGaAs S/D. Device FabricationThe fabrication process flow for In 0.7 Ga 0.3 As channel n-MOSFETs with self-aligned Ni-InGaAs contacts is summarized and illustrated in Fig. 1. 2-in. p-type (N A $1 Â 10 19 cm À3 ) InP wafer was used as starting substrates. A 500 nm thick In 0.53 Ga 0.47 As with p-type (Zn doped) doping concentration N A of 2 Â 10 17 cm À3 and a 20 nm thick In 0.7 Ga 0.3 As with N A of 2 Â 10 16 cm À3 were sequentially grown. After pregate cleaning using HCl and NH 4 OH solution, (NH 4 ) 2 S solution was used to passivate the In 03.7 Ga 0.3 As surface for suppression of surface oxidation. The sample was then quickly loaded into an atomic layer deposition (ALD) tool and $7 nm of Al 2 O 3 was deposited. TaN gate electrode (100 nm thick) was deposited by sputtering, patterned by optical lithography and etched by Cl 2 -based plasma.After gate stack formation, one batch of devices (implanted devices) w...

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mentioning

confidence: 99%

Reduction of Off-State Leakage Current in In0.7Ga0.3As Channel n-MOSFETs with Self-Aligned Ni-InGaAs Contact Metallization

Zhang

Guo

Lin

et al. 2011

Electrochem. Solid-State Lett.

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“…InSb semiconductor has the highest electron and hole mobilities and also has the highest electron saturation velocity of all semiconductors. The electron mobility in InSb quantum well is in excess of 30,000 cm 2 /Vs which is five times higher than that of state-of-the-art uncooled GaAs material [261][262][263][264][265].…”

Section: Developments In Indium Phosphide Hemtsmentioning

confidence: 99%

A review of InP/InAlAs/InGaAs based transistors for high frequency applications

Ajayan

Nirmal

2015

Superlattices and Microstructures

117

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“…In addition, the application of compressive strain into antimonide materials can be regarded as quite effective in boosting the hole mobility. 15,242) There have recently been many reports on GaSb, 178,182,202,[243][244][245][246][247][248] InGaSb, 168,170,247,[249][250][251][252] and InSb [253][254][255] p-MOSFETs. Some of them have exhibited fairly good hole effective mobility.…”

Section: Iii-v Cmosmentioning

confidence: 99%

III–V/Ge channel MOS device technologies in nano CMOS era

Takagi

Zhang

Suh

et al. 2015

Jpn. J. Appl. Phys.

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CMOS utilizing high-mobility III–V/Ge channels on Si substrates is expected to be one of the promising devices for high-performance and low power advanced LSIs in the future, because of its enhanced carrier transport properties. However, there are many critical issues and difficult challenges for realizing III–V/Ge-based CMOS on the Si platform such as (1) the formation of high-crystal-quality Ge/III–V films on Si substrates, (2) gate stack technologies to realize superior MOS/MIS interface quality, (3) the formation of a source/drain (S/D) with low resistivity and low leakage current, (4) process integration to realize ultrashort channel devices, and (5) total CMOS integration including Si CMOS. In this paper, we review the recent progress in III–V/Ge MOS devices and process technologies as viable approaches to solve the above critical problems on the basis of our recent research activities. The technologies include MOS gate stack formation, high-quality channel formation, low-resistance S/D formation, and CMOS integration. For the Ge device technologies, we focus on the gate stack technology and Ge channel formation on Si. Also, for the III–V MOS device technologies, we mainly address the gate stack technology, III–V channel formation on Si, the metal S/D technology, and implementation of these technologies into short-channel III–V-OI MOSFETs on Si substrates. On the basis of the present status of the achievements, we finally discuss the possibility of various CMOS structures using III–V/Ge channels.

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High-performance InSb based quantum well field effect transistors for low-power dissipation applications

Cited by 12 publications

References 5 publications

Reduction of Off-State Leakage Current in In0.7Ga0.3As Channel n-MOSFETs with Self-Aligned Ni-InGaAs Contact Metallization

Reduction of Off-State Leakage Current in In0.7Ga0.3As Channel n-MOSFETs with Self-Aligned Ni-InGaAs Contact Metallization

A review of InP/InAlAs/InGaAs based transistors for high frequency applications

III–V/Ge channel MOS device technologies in nano CMOS era

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