High-performance implementation of regular and easily scalable sorting networks on an FPGA

Sklyarov, Valery; Skliarova, Iouliia

doi:10.1016/j.micpro.2014.03.003

Cited by 45 publications

(25 citation statements)

References 17 publications

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“…Attributes for each object are read from memory by the PL, sorted using fast and highly parallel iterative networks from [17], and the sorted attributes are copied back to the same memory.…”

Section: The Methodsmentioning

confidence: 99%

“…Software/hardware co-design for data sort is studied in detail in [14][15][16][17][18][19]. It is shown in [17] that the fastest known even-odd merge and bitonic merge circuits [20] are very resource consuming and can only be used effectively in existing FPGAs for sorting very small data sets.…”

Section: Introductionmentioning

confidence: 99%

“…It is shown in [17] that the fastest known even-odd merge and bitonic merge circuits [20] are very resource consuming and can only be used effectively in existing FPGAs for sorting very small data sets. An alternative solution is based on an iterative even-odd transition network [17] that is very regular and can be implemented efficiently in FPGAs for larger data sets. Besides, for many practical applications the effective throughput is higher than in other known networks, which is demonstrated in [17] on the results of numerous experiments in FPGA.…”

Section: Introductionmentioning

confidence: 99%

“…An alternative solution is based on an iterative even-odd transition network [17] that is very regular and can be implemented efficiently in FPGAs for larger data sets. Besides, for many practical applications the effective throughput is higher than in other known networks, which is demonstrated in [17] on the results of numerous experiments in FPGA. The size of blocks (subsets of data) sorted in FPGA is increased but it is still small and constrained by the available FPGA resources.…”

Section: Introductionmentioning

confidence: 99%

“…Additional experiments were done with the expensive prototyping system VC 707 from Xilinx [21], but even using the advanced FPGA XC7VX485T from Xilinx Virtex-7 family, the maximum size N of one block is limited to 4,096 32-bit items. To sort more data items with significantly cheaper microchips, we propose to split the problem into two parts [17], one executed in the reconfigurable logic and the other in software running on embedded high-performance processors. Zynq All Programmable Systems-on-Chip (APSoC) are very appropriate for such decomposition.…”

Section: Introductionmentioning

confidence: 99%

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Hardware accelerators for information retrieval and data mining

Sklyarov

Skliarova

Silva

et al. 2015

2015 International Conference on Information and Communication Technology Research (ICTRC)

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Many algorithms in informatics require a set of objects with similar properties to be grouped (clustered) on the basis of some predefined criteria. The proposed technique involves hierarchical merging in which software, responsible for solving the entire problem, is enhanced with highly parallel networks in hardware accelerators. Additional improvements are achieved with the aid of support methods that are sort and verification of object intersections that may also be autonomously used for other types of information processing and database management. It is shown and experimentally proved that the proposed solutions are efficient. They can be used in such areas as health care, statistical data manipulation and so on.

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Section: The Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Hardware accelerators for information retrieval and data mining

Sklyarov

Skliarova

Silva

et al. 2015

2015 International Conference on Information and Communication Technology Research (ICTRC)

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A radix sorting parallel algorithm suitable for graphic processing unit computing

Xiao

Guo

et al. 2020

Concurrency and Computation

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Radix sorting is an essential basic data processing operation in many computer fields. It has important practical significance to accelerate its performance through Graphic Processing Unit (GPU). The heterogeneous parallel computing technology attracts much attention and is widely applied for its effective computation efficiency and parallel real-time data processing capability. Taking advantage of the parallelism of GPU in numerical computation processing, a parallelization design method of the Binary_Least Significant Digit (LSD) first Radix Sorting (B_LSD_RS) algorithm based on Open Computing Language (OpenCL) is proposed. The radix sorting algorithm is divided into multiple kernel tasks, and the kernels are sequentially controlled by the event information transfer. The parallel algorithm is implemented and verified on the GPU + CPU heterogeneous platform. The experimental results show that compared with the performance of the B_LSD_RS sequential algorithm based on AMD Ryzen5 1600X CPU, B_LSD_RS parallel algorithm based on Open Multi-Processing (OpenMP) and B_LSD_RS parallel algorithm based on Compute Unified Device Architecture (CUDA), the B_LSD_RS parallel algorithm based on OpenCL obtained 28.86 times, 11.01 times and 2.14 times speedup in the NVIDIA GTX 1070 computing platform respectively, not only achieves high performance but also achieves performance portability among different GPU computing platforms.

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Engineering faster sorters for small sets of items

2020

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Sorting a set of items is a task that can be useful by itself or as a building block for more complex operations. That is why a lot of effort has been put into finding sorting algorithms that sort large sets as efficiently as possible. But the more sophisticated and complex the algorithms become, the less efficient they are for small sets of items due to large constant factors. A relatively simple sorting algorithm that is often used as a base case sorter is insertion sort, because it has small code size and small constant factors influencing its execution time. We aim to determine if there is a faster way to sort small sets of items to provide an efficient base case sorter. We looked at sorting networks, at how they can improve the speed of sorting few elements, and how to implement them in an efficient manner using conditional moves. Since sorting networks need to be implemented explicitly for each set size, providing networks for larger sizes becomes less efficient due to increased code sizes. To also enable the sorting of slightly larger base cases, we adapted sample sort to Register Sample Sort, to break down those larger sets into sizes that can in turn be sorted by sorting networks. From our experiments we found that when sorting only small sets of integers, the sorting networks outperform insertion sort by a factor of at least 1.76 for any array size between six and 16, and by a factor of 2.72 on average across all machines and array sizes. When integrating sorting networks as a base case sorter into Quicksort, we achieved far less performance improvements over using insertion sort, which is probably due to the networks having a larger code size and cluttering the L1 instruction cache. The same effect occurs when including Register Sample Sort as a base case sorter for IPS4o. But for x86 machines that have a larger L1 instruction cache of 64 KiB or more, we obtained speedups of 12.7% when using sorting networks as a base case sorter in std::sort, and of 5%–6% when integrating Register Sample Sort as a base case sorter into IPS4o, each in comparison to using insertion sort as the base case sorter. In conclusion, the desired improvement in speed could only be achieved under special circumstances, but the results clearly show the potential of using conditional moves in the field of sorting algorithms.

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High-performance implementation of regular and easily scalable sorting networks on an FPGA

Cited by 45 publications

References 17 publications

Hardware accelerators for information retrieval and data mining

Hardware accelerators for information retrieval and data mining

A radix sorting parallel algorithm suitable for graphic processing unit computing

Engineering faster sorters for small sets of items

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