High performance IIR filter implementation on FPGA

Datta, Debarshi; Dutta, Himadri Sekhar

doi:10.1186/s43067-020-00025-4

Cited by 15 publications

(4 citation statements)

References 12 publications

(11 reference statements)

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“…The efficiency of the algorithm that is being utilized in any system or design requires it to be more efficient. In such instances, using the pipelining technique to measure the algorithm's efficiency is highly recommended [21,28,29]. The author examines pipelined and non-pipelined FIR and IIR filters utilizing a full comparative investigation of the designs using several accessible FPGAs.…”

Section: Related Workmentioning

confidence: 99%

Design and Implementation of Two- Dimensional Pipelined& Parallel FIR Filter Architectures

Singh

Kumar

2022

Preprint

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This paper aims at designing and implementation of two dimensional pipelining, fine-grain pipelining, parallel processing and combined pipelining and parallel processing architecture for FIR filter using VHDL (Very High Speed Integrated Circuit Hardware Description Language). These specific architectures significantly reduce the delay and the power consumption of the filter. Sampling frequency for the proposed designs is given in this paper. Rectangular window method is used for calculating Filter coefficients for the proposed two dimensional FIR filter architectures. The proposed filters are compared with the existing FIR filter in respect to area, operational speed, power consumption and delay. The proposed designs of the FIR digital filters provides an optimum output with 81% increase in speed of operation and up to 75% reduction in power consumption when compare to the existing architectures. Implementation of the FIR filter is carried out by using VHDL codes. Simulation and synthesis have been executed on Artix-7 FPGA series with the target device (xc7a35t-cpg236) speed grade-I using Xilinx Vivado 2015.2 version.

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Section: Related Workmentioning

confidence: 99%

Design and Implementation of Two- Dimensional Pipelined& Parallel FIR Filter Architectures

Singh

Kumar

2022

Preprint

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“…In most cases, FIR filters are efficient to implement, have a low number of finite precision errors, and are stable and linear in phase. The computational complexity is higher than that of an IIR filter by a significant margin [1]. Additionally, there is a reduction in the number of coefficients and the amount of space needed for an IIR filter.…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable Architecture for Noise Cancellation in Acoustic Environment Using Single Multiply Accumulate Adaline Filter

2023

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The creation of multiple applications with a higher level of complexity has been made possible by the usage of artificial neural networks (ANNs). In this research, an efficient flexible finite impulse response (FIR) filter structure called ADALINE (adaptive linear element) that makes use of a MAC (multiply accumulate) core is proposed. The least mean square (LMS) and recursive least square (RLS) algorithms are the most often used methods for maximizing filter coefficients. Despite outperforming the LMS, the RLS approach has not been favored for real-time applications due to its higher design arithmetic complexity. To achieve less computation, the fundamental filter has utilized an LMS-based tapping delay line filter, which is practically a workable option for an adaptive filtering algorithm. To discover the undiscovered system, the adjustable coefficient filters have been developed in the suggested work utilizing an optimal LMS approach. The 10-tap filter being considered here has been analyzed and synthesized utilizing field programmable gate array (FPGA) devices and programming in hardware description language. In terms of how well the resources were used, the placement and postrouting design performed well. If the implemented filter architecture is compared with the existing filter architecture, it reveals a 25% decrease in resources from the existing one and an increase in clock frequency of roughly 20%.

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“…Processors, DSPs, and FPGAs, provide an appropriate platform for processing digital signals of this type [11]. Many new designs and software products have recently been proposed using field-programmable gate arrays (FPGAs) as hardware for DSP systems because of the technology's extremely high performance and flexibility [12]. Now that FPGAs are equipped with gigabit serial communications, memory interfaces, embedded processors, and a wide range of core firmware modules, this is even more relevant than before [13].…”

Section: Introductionmentioning

confidence: 99%

Implementation of VLSI on Signal Processing-Based Digital Architecture Using AES Algorithm

Marimuthu¹,

Rajendran²,

Radhakrishnan³

et al. 2023

Computers, Materials &Amp; Continua

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Continuous improvements in very-large-scale integration (VLSI) technology and design software have significantly broadened the scope of digital signal processing (DSP) applications. The use of application-specific integrated circuits (ASICs) and programmable digital signal processors for many DSP applications have changed, even though new system implementations based on reconfigurable computing are becoming more complex. Adaptable platforms that combine hardware and software programmability efficiency are rapidly maturing with discrete wavelet transformation (DWT) and sophisticated computerized design techniques, which are much needed in today's modern world. New research and commercial efforts to sustain power optimization, cost savings, and improved runtime effectiveness have been initiated as initial reconfigurable technologies have emerged. Hence, in this paper, it is proposed that the DWT method can be implemented on a fieldprogrammable gate array in a digital architecture (FPGA-DA). We examined the effects of quantization on DWT performance in classification problems to demonstrate its reliability concerning fixed-point math implementations. The Advanced Encryption Standard (AES) algorithm for DWT learning used in this architecture is less responsive to resampling errors than the previously proposed solution in the literature using the artificial neural networks (ANN) method. By reducing hardware area by 57%, the proposed system has a higher throughput rate of 88.72%, reliability analysis of 95.5% compared to the other standard methods.

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High performance IIR filter implementation on FPGA

Cited by 15 publications

References 12 publications

Design and Implementation of Two- Dimensional Pipelined& Parallel FIR Filter Architectures

Design and Implementation of Two- Dimensional Pipelined& Parallel FIR Filter Architectures

Reconfigurable Architecture for Noise Cancellation in Acoustic Environment Using Single Multiply Accumulate Adaline Filter

Implementation of VLSI on Signal Processing-Based Digital Architecture Using AES Algorithm

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High performance IIR filter implementation on FPGA

Cited by 15 publications

References 12 publications

Design and Implementation of Two- Dimensional Pipelined&amp; Parallel FIR Filter Architectures

Design and Implementation of Two- Dimensional Pipelined&amp; Parallel FIR Filter Architectures

Reconfigurable Architecture for Noise Cancellation in Acoustic Environment Using Single Multiply Accumulate Adaline Filter

Implementation of VLSI on Signal Processing-Based Digital Architecture Using AES Algorithm

Contact Info

Product

Resources

About

Design and Implementation of Two- Dimensional Pipelined& Parallel FIR Filter Architectures

Design and Implementation of Two- Dimensional Pipelined& Parallel FIR Filter Architectures