Design and Implementation of Two- Dimensional Pipelined& Parallel FIR Filter Architectures

Abstract

This paper aims at designing and implementation of two dimensional pipelining, fine-grain pipelining, parallel processing and combined pipelining and parallel processing architecture for FIR filter using VHDL (Very High Speed Integrated Circuit Hardware Description Language). These specific architectures significantly reduce the delay and the power consumption of the filter. Sampling frequency for the proposed designs is given in this paper. Rectangular window method is used for calculating Filter coefficients for the proposed two dimensional FIR filter architectures. The proposed filters are compared with the existing FIR filter in respect to area, operational speed, power consumption and delay. The proposed designs of the FIR digital filters provides an optimum output with 81% increase in speed of operation and up to 75% reduction in power consumption when compare to the existing architectures. Implementation of the FIR filter is carried out by using VHDL codes. Simulation and synthesis have been executed on Artix-7 FPGA series with the target device (xc7a35t-cpg236) speed grade-I using Xilinx Vivado 2015.2 version.