2016 IEEE International Electron Devices Meeting (IEDM) 2016
DOI: 10.1109/iedm.2016.7838536
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High performance Ge junctionless gate-all-around NFETs with simultaneous I<inf>on</inf> =1235 μA/μm at V<inf>ov</inf>=V<inf>ds</inf>=1V, SS=95 mV/dec, high I<inf>on</inf>/I<inf>off</inf>=2×106, and reduced noise power density using S/D dopant recovery by selective laser annealing

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Cited by 2 publications
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“…The CET is approximation 1.3 nm. The optimized selective laser annealing further lowered S/D resistance by increasing active dopant concentration (∼2E20 cm −3 ) at S/D using the Pt as the mask for the gate stack [17,18]. Finally, the NiGe contact was formed by sputtering and PMA with FGA at 300 °C for 1 min to reduce the contact resistance.…”
Section: Devices Fabricationmentioning
confidence: 99%
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“…The CET is approximation 1.3 nm. The optimized selective laser annealing further lowered S/D resistance by increasing active dopant concentration (∼2E20 cm −3 ) at S/D using the Pt as the mask for the gate stack [17,18]. Finally, the NiGe contact was formed by sputtering and PMA with FGA at 300 °C for 1 min to reduce the contact resistance.…”
Section: Devices Fabricationmentioning
confidence: 99%
“…Figure 10 shows the benchmark of the I on per stack versus SS for group IV nGAAFETs [7,17,[25][26][27][28][29][30][31][32][33]. The optimized device achieves low SS=76 mV/dec, and the high I on of 15.2 μA per stack at V OV =V DS =0.5 V. The device has competitive performance in group IV nGAAFETs.…”
Section: Benchmarkmentioning
confidence: 99%