High-performance gate-all-around polycrystalline silicon nanowire with silicon nanocrystals nonvolatile memory

Abstract

Nonvolatile memory (NVM) that is based on gate-all-around (GAA) and polycrystalline silicon (poly-Si) nanowires structure with silicon nanocrystals (NCs) as the storage nodes is demonstrated. The GAA poly-Si–SiO2–Si3N4–SiO2–poly-Si (SONOS) NVMs are also fabricated and compared. The GAA NCs NVMs have a 4.2 V of threshold voltage shift at 18 V for 1 ms, and are faster than the GAA SONOS NVMs do. In reliability studies, this NVM shows superior endurance after 104 program/erase (P/E) cycles, and loses only 14% of its charges lose after ten years at 85 °C.

Thin Film Polycrystalline Silicon Nanowire Biosensors

“…The characteristics are linear at low currents, with subthreshold slopes in the range of 2.3−3.0 V/decade. Polysilicon nanowires have recently been found to be very promising for nonvolatile memory design, 21,22 for the design of inexpensive electrochemical sensors, 23 and as sensitive nanowire-based biosensors. 24,25 The sensitivity of the nanowire biosensor is controlled by the doping concentration in the nanowire.…”

Applications of Nanotechnology in Next-Generation Nonvolatile Memories

“…The device fabricated by Hung et al [48] has shown threshold voltage shifts of 2-3 V for write voltage of ±15 V and stress time of 0.1 s, for both electron and hole charging. For the same write voltage and an erase voltage of −23 V for 0.1 s, they tested the device for its retention characteristics.…”

“…In a very recent work (2011), Hung et al [48] have reported the memory performance of a SPC poly-Si nanowire GAA MOSFET NVM device, with 2 nm Si-ncs embedded in the nitride layer of 8 nm thickness, in an oxide (12 nm)-nitride (8 nm)-oxide (12 nm) stack. The in situ-doped poly-Si nanowires were rectangular in cross section with a width of 60 nm and a height of 25 nm [48].…”

“…The in situ-doped poly-Si nanowires were rectangular in cross section with a width of 60 nm and a height of 25 nm [48].…”

Enhancement of programming speed on gate-all-around poly-silicon nanowire nonvolatile memory using self-aligned NiSi Schottky barrier source/drain

“…9,10 However, typical gate voltage in GAA SONOS memory of 15-18 V is quite high for programming and erasing, even though an operational voltage of $20 V is acceptable in current NAND flash memory cells. 11,12 A reduction in the operational voltage is an important target in regard to ameliorating power consumption for future GAA NWs in nonvolatile SONOS memory.…”