High-performance FPGA implementation of DES using a novel method for implementing the key schedule

Pipelining Concept for Low Power DES Implementation

“…The system designed by M. McLoone and J. McCanny [4] used 6446 slices for the operation. Further, the works designed by Praveen K., et.al.…”

“…It works through a series of 16 rounds and each round consists of the same operations, ie, bitshuffling, non-linear substitutions & exclusive-OR operations. This structure of DES Algorithm makes it suitable for pipelining and the 16 rounds of the algorithm are unrolled and pipelined using additional registers [3], [4].…”

Biomedical Image Transmission Based on Modified Feistal Algorithm

“…These operations make use of tables PC1 and PC2 which are permuted choice 1 and permuted choice 2 [6].The 8 bits of 64 bits is discarded by PC1 .The remaining 56 bits are permuted and assigned to two 28-bit variables C and D; and then a cyclic shift operation is carried out on each half. Both C and D are rotated either 1 or 2 bits for 16 iterations, and 48 bit keys (Ki) are selected from the concatenated result.…”

“…The ECB mode of DES algorithm is implemented in this paper as it can be easily pipelined [8].This pipelined DES design increases the speed and throughput of DES significantly [6]. A combinational digital circuit can be converted into a pipelined design by dividing it into stages and inserting buffers (registers) at proper places [2].…”

“…For the 16-stage pipelined DES design, the sub keys are pre-computed and it is necessary to control the time at which the sub keys are available to each function f block [6]. This is accomplished by addition of an array of D flip flops that delays the individual sub-keys by required amount [6,9].…”