2022
DOI: 10.1109/led.2021.3128940
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High-Performance Dual Gate Amorphous InGaZnO Thin Film Transistor With Top Gate to Drain Offset

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Cited by 9 publications
(1 citation statement)
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“…Insufficient carrier mobility is caused by the high interface trap density and defect centers in the channel and dielectric, resulting in a reduction in current driving capabilities and threshold voltage instability [5][6][7]. Many structural optimizations such as self-aligned top gate structure [8], double gate structure [9,10], vertical structure, and multigate structure are implemented to improve the electrical performance of the device. Nevertheless, the process steps required to fabricate the above structures are complex and not very cost-effective.…”
Section: Introductionmentioning
confidence: 99%
“…Insufficient carrier mobility is caused by the high interface trap density and defect centers in the channel and dielectric, resulting in a reduction in current driving capabilities and threshold voltage instability [5][6][7]. Many structural optimizations such as self-aligned top gate structure [8], double gate structure [9,10], vertical structure, and multigate structure are implemented to improve the electrical performance of the device. Nevertheless, the process steps required to fabricate the above structures are complex and not very cost-effective.…”
Section: Introductionmentioning
confidence: 99%