High performance DES encryption in Virtex/sup TM/ FPGAs using JBits/sup TM/

Patterson, Cameron

doi:10.1109/fpga.2000.903398

Cited by 46 publications

(39 citation statements)

References 6 publications

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“…In the literature there are several implementations of the three most widely used cryptographic algorithms (DES, AES and MD5) in either software, or hardware; the hardware approaches are tailored to both ASICs and FPGAs [4], [5], [6], [7], [8].…”

Section: Related Workmentioning

confidence: 99%

On the Power Consumption of Security Algorithms Employed in Wireless Networks

Meintanis

Papaefstathiou

2009

2009 6th IEEE Consumer Communications and Networking Conference

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Supporting high levels of security in wireless networks is a challenging issue because of the specific problems this environment poses; the provided security by small mobile systems, such as PDAs and mobile phones, is often restricted by their limited battery power and their limited processing power. Driven by these restrictions, the designer will have to decide whether to implement the wireless network security schemes in software or to add special purpose hardware units to the system, executing those CPU intensive tasks. This paper demonstrates and compares the Hardware and Software implementations of a number of widely used security applications employed in wireless networks. We measured the total energy consumption for each security algorithm when implemented in reconfigurable hardware devices and we compared it with the total energy consumption of the equivalent software applications. We demonstrate, that the hardware implementations on a state-of-the-art FPGA are significantly faster while they consume three orders of magnitude less power when compared with the software implementations executed on a state-of-the-art hard-core CPU which is embedded in the same FPGA device.

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Section: Related Workmentioning

confidence: 99%

On the Power Consumption of Security Algorithms Employed in Wireless Networks

Meintanis

Papaefstathiou

2009

2009 6th IEEE Consumer Communications and Networking Conference

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“…A single-chip implementation of an iterative DES algorithm on a FPGA platform using 224 combinational logic blocks (CLBs) and 54 input/output blocks (IOBs) is presented in [19]. Patterson [20] presented a FPGA implementation of DES using Java API bit stream support for computing the key schedule entirely using software resulting in a throughput of 10 Gigabits per second. Another FPGA-based implementation of DES is presented in [21].…”

Section: Introductionmentioning

confidence: 99%

Smart as a Cryptographic Processor

Kanchi¹,

Tabrizi²,

Hayden³

2016

Computer Science &Amp; Information Technology ( CS &Amp; IT )

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“…Through RTR, more sections of an application can be mapped into hardware and thus, despite reconfiguration time overhead, a potential for an overall performance improvement is provided. RTR can be applied on different phases of the design process, according to the granularity of the reconfigurable blocks, which may be complex functions [9], simple RTL components [1] or LUTs [11]. The reconfiguration data can be stored inside the reconfigurable device [10] or transfered from an embedded or host processor [9].…”

Section: Introductionmentioning

confidence: 99%

“…RTR can be applied on different phases of the design process, according to the granularity of the reconfigurable blocks, which may be complex functions [9], simple RTL components [1] or LUTs [11]. The reconfiguration data can be stored inside the reconfigurable device [10] or transfered from an embedded or host processor [9]. The underlying architecture can be traditional FPGAs or special purpose architectures [6,11,12], supporting very fast reconfiguration.…”

Section: Introductionmentioning

confidence: 99%

High-level synthesis with reconfigurable datapath components

Economakos

2006

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

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High-level synthesis is becoming more popular as design densities keep increasing, especially in the ASIC design world. Although FPGA design follows ASIC design methodologies and FPGA densities are increasing too, programmable devices also offer the advantage of partial reconfiguration, which allows an algorithm to be partially mapped into a small and fixed FPGA device that can be reconfigured at run time, as the mapped application changes its requirements. This paper presents a novel resource constrained high-level synthesis scheduling heuristic, which utilizes reconfigurable datapath components. The resulting schedule can be shortened so as the gain in clock cycles can overcome the timing overhead of reconfiguration. The main advantage of the proposed methodology is that through run time reconfiguration, more complicated algorithms can be mapped into smaller devices without speed degradation.

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High performance DES encryption in Virtex/sup TM/ FPGAs using JBits/sup TM/

Cited by 46 publications

References 6 publications

On the Power Consumption of Security Algorithms Employed in Wireless Networks

On the Power Consumption of Security Algorithms Employed in Wireless Networks

Smart as a Cryptographic Processor

High-level synthesis with reconfigurable datapath components

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