High-performance DCT architecture based on angle recoding CORDIC and Scale-Free Factor

Hoang, Trong-Thuc; Nguyen, Hong-Thu; Nguyen, Xuan-Thuan; Pham, Cong‐Kha; Le, Duc-Hung

doi:10.1109/cce.2016.7562636

Cited by 5 publications

(4 citation statements)

References 10 publications

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“…Furthermore, the six implementations were built and verified on an Altera FPGA Stratix IV and Stratix II with the chipsets of EP4SGX530KH40C2 and EP2SGX90EF115C3, respectively. Table I gives the SFGs' results in comparison with other works including our previous work in [16]. Table II and Table III give the FPGAs' results on Stratix IV and Stratix II, respectively.…”

Section: Results and Comparisonmentioning

confidence: 99%

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Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC

Hoang

Pham

2018

IEICE Electron. Express

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In this paper, the minimum adder-delay Discrete Cosine Transform (DCT) architecture is proposed using the Adaptive CORDIC (ACor) algorithm with fixed-rotation implementations. The proposed method has six different versions differ from the number of DCT point, i.e., 8-point (8p), 16-point (16p), and 32-point (32p), and the number of ACor stages, i.e., 2-Stage (2S) and 3-Stage (3S). The Altera Stratix IV and Stratix II FPGAs were used to built and verified the implementations. The 2S designs of 8p, 16p, and 32p DCT achieved the timing performances of four, five, and six adder-delay results, respectively. The proposed method was proven to have the best timing performances, good accuracy results, and adequate resources cost in comparison with other recent works.

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Section: Results and Comparisonmentioning

confidence: 99%

“…In this paper, the proposed DCT architecture was developed based on the ACor algorithm [15] and the extension of the previous work [16]. Six different versions were implemented based on the number of DCT-point, i.e., 8-point (8p), 16-point (16p), and 32-point (32p), and the number of ACor stages, i.e., 2-Stage (2S) and 3-Stage (3S).…”

Section: Introductionmentioning

confidence: 99%

Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC

Hoang

Pham

2018

IEICE Electron. Express

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“…The linear, circular, and hyperbolic CORDIC rotations, the use of BAR guarantees more than 50% reduction of elementary CORDIC rotations provided the scaling factor needs not be kept constant. An on-line CORDIC algorithm with a constant scale factor and latency independent design has been derived through the extension of derivative simplified metrics [12]. Angle quantization (AQ) [13] is used as a design index for vector rotational operation, where the rotational angle with a unified design framework for cost-effective low-latency rotational algorithms and architectures.…”

Section: Introductionmentioning

confidence: 99%

LH-CORDIC: Low Power FPGA Based Implementation of CORDIC Architecture

Inguva¹,

Seventiline²

2019

IJIES

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The coordinate rotation digital computer (CORDIC) is a class of shift-add algorithms for rotating vectors in plane. Several techniques use the trigonometry function to compute the digital waves, but that requires expensive memory usage. Due to the flexible characteristics, CORDIC is best alternative and allows high quantization accuracy by maximum word length. The linear-rate convergence creates the major problem in CORDIC algorithm with the source of word-length and iteration speed. The power consumption also a major issue here to affects the performance by array of shift-add operations. For further enhancement, in this paper, we propose a low power and high speed CORDIC (LH-CORDIC) design with an improved power control and hardware reduction techniques. We employ the canonical signed-digit (CSD) technique and Hcub algorithm for reducing the number of shifters and adder/subtractor in the design. Then, we propose an adder based on the advanced Boolean logic technique. These three techniques are used to redesign the entire CORDIC logic stages thereby contributing in power consumption reduction. The functionality of proposed LH-CORDIC algorithm is assessed through FPGA implementations. The simulation result shows that the proposed method has higher frequency of 78.91%, 83.42%, 79.89% and 77.01% when compared with conventional CORDIC method.

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“…The second axe consist on improve the DCT in terms of power consumption ( [5], [6], [7]). In fact, it is well-known that DCT is one of the computationally intensive transforms since it requires many multiplications and additions.…”

Section: Introductionmentioning

confidence: 99%

High Precision DCT CORDIC Architectures for Maximum PSNR

Saad¹,

Hachaı̈chi²,

Lahbib³

et al. 2017

ijacsa

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Abstract-This paper proposes two optimal Cordic Loeffler based DCT (Discrete Cosine Transform algorithm) architectures: a fast and low Power DCT architecture and a high PSNR DCT architecture. The rotation parameters of CORDIC angles required for these architectures have been calculated using a MATLAB script. This script allows the variation of the angle's precision from 10 −1 to 10 −4 . The experimental results show that the fast and low Power DCT architecture correponds to the precision 10 −1 . Its complexity is even lower than the BinDCT which is a reference in terms of low complexity and its power has been enhanced in comparison with the conventional Cordic Loeffler DCT by 12 mW. The experimental results also show that the high PSNR DCT architecture corresponds to the precision 10 −3 for which the PSNR has been improved by 6.55 dB in comparison with the conventional Cordic Loeffler DCT. Then, the hardware implementation and the generated RTL of some required Cordics are presented.

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High-performance DCT architecture based on angle recoding CORDIC and Scale-Free Factor

Cited by 5 publications

References 10 publications

Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC

Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC

LH-CORDIC: Low Power FPGA Based Implementation of CORDIC Architecture

High Precision DCT CORDIC Architectures for Maximum PSNR

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