High performance collective communication-aware 3D Network-on-Chip architectures

Joardar, Biresh Kumar; Duraisamy, Karthi; Pande, Partha Pratim

doi:10.23919/date.2018.8342223

Cited by 10 publications

(6 citation statements)

References 15 publications

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“…Despite the benefits brought by SMART NoCs, due to the large control overhead and throughput loss in some cases, some improved works (e.g., [7], [9], [10], [21]- [23]) are proposed to upgrade the performance of SMART. In addition, in light of this communication advantage of S-MART techniques, many studies (e.g., [8], [24], [25]) employ SMART design as the communication fabric of multi/manycore systems. However, there are few studies to optimize the SMART communication performance with the consideration of contention reduction (i.e., N c ).…”

Section: End-to-end Latency In Smart Nocsmentioning

confidence: 99%

Contention Minimization in Emerging SMART NoC via Direct and Indirect Routes

Chen

Zhou

et al. 2021

IEEE Trans. Comput.

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Section: End-to-end Latency In Smart Nocsmentioning

confidence: 99%

Contention Minimization in Emerging SMART NoC via Direct and Indirect Routes

Chen

Zhou

et al. 2021

IEEE Trans. Comput.

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“…As long as the SLT path is pre-built, SMART enables the exclusive transmission of the SLT path by avoiding buffering at intermediate routers. Recently, many research works (e.g., [3,8,10,30,41]) improve SMART performance and employ SMART techniques to build new works (e.g., [11,21,24,27]). Distinct from wormhole NoC of Fig.…”

Section: Slt Noc Adoptionmentioning

confidence: 99%

Partial order based non-preemptive communication scheduling towards real-time networks-on-chip

Chen

Zhou

et al. 2021

Proceedings of the 36th Annual ACM Symposium on Applied Computing

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“…• Modern techniques are presented to ensure a single cycle transfer between distant tiles. For example, wireless links are used in [36], optical links are used in [37], and 3D technologies are used in [38]. These techniques could be integrated with our approach to accomplish the required single cycle operation.…”

Section: N Oc 2 : An Efficient Noc Interfacing Approachmentioning

confidence: 99%

NoC²: An Efficient Interfacing Approach for Heavily-Communicating NoC-Based Systems

et al. 2020

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Current research in interfacing clusters within Hierarchical Networks-on-Chip (HNoC) as well as interfacing NoC-based systems adopts a centralized approach. In this approach, a specific Processing Element (PE) acts as a gateway between interfacing peripherals and the rest of NoC elements. This paper evaluates this approach and show that it is not optimal for handling the inter-NoC communication. Routing inter-NoC traffic through a system to its gateway PE deteriorates the network performance. Results show that both the throughput and latency of the centralized approach degrade with the increase in the inter-NoC traffic bandwidth. To alleviate this, we propose a novel distributed approach, which separates the inter-NoC traffic from the intra-NoC one. Our approach relies on distributed buffers to allow PEs to efficiently communicate with the interfacing peripheral. We evaluate our approach against other interfacing ones using synthetic traffic as well as real benchmark applications. Our evaluation covers the whole system performance as well as its inter-and intra-NoC parts. Results prove that the proposed approach outperforms previous interfacing ones in terms of throughput and latency. The proposed approach significantly enhances the inter-NoC performance without any deterioration in the intra-NoC one. Considering the inter-NoC performance, we achieve a throughput that is close to the maximum possibly attainable one. Other approaches show major performance degradation, reaching as low as 10% of this maximum attainable throughput. INDEX TERMS Hierarchical Networks-on-Chip (HNoC), Inter-NoC communication, Intra-NoC communication, NoC benchmarks, NoC Ethernet, NoC high-speed interfacing, NoC Time Division Multiple Access (TDMA), NoC traffic.

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High performance collective communication-aware 3D Network-on-Chip architectures

Cited by 10 publications

References 15 publications

Contention Minimization in Emerging SMART NoC via Direct and Indirect Routes

Contention Minimization in Emerging SMART NoC via Direct and Indirect Routes

Partial order based non-preemptive communication scheduling towards real-time networks-on-chip

NoC²: An Efficient Interfacing Approach for Heavily-Communicating NoC-Based Systems

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High performance collective communication-aware 3D Network-on-Chip architectures

Cited by 10 publications

References 15 publications

Contention Minimization in Emerging SMART NoC via Direct and Indirect Routes

Contention Minimization in Emerging SMART NoC via Direct and Indirect Routes

Partial order based non-preemptive communication scheduling towards real-time networks-on-chip

NoC2: An Efficient Interfacing Approach for Heavily-Communicating NoC-Based Systems

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Product

Resources

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NoC²: An Efficient Interfacing Approach for Heavily-Communicating NoC-Based Systems