High Performance and Reliability Trench Gate Power MOSFET With Partially Thick Gate Oxide Film Structure (PTOx-TMOS)

Aoki, Takaaki; Tsuzuki, Yukio; Miura, S.; Okabe, Yoshifumi; Suzuki, Mikimasa; Kuroyanagi, A.

doi:10.1109/ispsd.2006.1666077

Cited by 8 publications

(4 citation statements)

References 2 publications

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“…6) The electric field at active edge is decreased by SiN liner. 7) Figure 7 shows the active edge profile of tunnel oxide. Oxide thickness of SiN liner process is 4 A ˚thicker than that of conventional process by SiN liner stress.…”

Section: Resultsmentioning

confidence: 99%

Improving the Cell Characteristics Using SiN Liner at Active Edge in 4 Gbits NAND Flash Memories

Kang¹,

Jang

Lee

et al. 2008

jjap

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We introduced the self aligned floating poly (SAP) process using the SiN liner at active edge to improve the cell characteristics of high density NAND flash memory devices. Capacitance and electric field at corner of active edge are related to on cell current and cell V th distributions. In a 70 nm design rule NAND flash cell, we can improve the about 0.2 mA of worst on cell current and cell V th distributions of 0.5 V respectively. Furthermore, we acknowledged that off cell current of SiN liner is lower than that of oxide liner.

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Section: Resultsmentioning

confidence: 99%

Improving the Cell Characteristics Using SiN Liner at Active Edge in 4 Gbits NAND Flash Memories

Kang¹,

Jang

Lee

et al. 2008

jjap

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“…Actually, the reduction rate of C i and C r in the devices A and A' differs and the C r /C i becomes larger with the widening of the W p as shown in TABLE I. Since C r is strongly associated with the SiO 2 thickness of the trench bottom (t ox ) [7][8][9], the relation between the C r /C i and the switching power dissipation as a parameter of the t ox and W p under the constant C i R g condition is investigated as shown in Figure 9 (b). Although a rough correlation is established by the east square method, each W p appears to have different slopes.…”

Section: Discussionmentioning

confidence: 99%

Investigation of correlation between device structures and switching losses of IGBTs

Machida

Sugiyama

Ishiko

et al. 2009

2009 21st International Symposium on Power Semiconductor Devices &Amp; IC's

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“…Other works [8][9][10] report significant threshold voltage shift and mobility degradation in power VDMOSFETs in the case of NBTS. Whereas, Aoki et al [11] treat the reliability study of trench gate power MOSFET with partially thick gate oxide film structure.…”

Section: Introductionmentioning

confidence: 99%

Negative Bias Temperature Stress Reliability in Trench-Gated P-Channel Power MOSFETs

Tallarico

Magnone

Barletta

et al. 2014

IEEE Trans. Device Mater. Relib.

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In this paper, we present the results of an experimental analysis of the degradation induced by negative bias temperature stress (NBTS) in trench-gated p-channel power MOSFETs. Threshold voltage and carrier mobility are affected by holes trapping in bulk oxide and interface states generation due to oxide electric field effects. A fast recovery phase occurs when gate bias is removed or reduced in order to measure the threshold voltage. Hence, various techniques for evaluating threshold voltage shift are adopted in order to highlight the differences in the dynamics of degradation. We investigate the influence of gate bias level during the stress. Moreover, with the help of recovery studies, we try to distinguish the impact of interface states generation and charge trapping on the NBTS degradation.

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High Performance and Reliability Trench Gate Power MOSFET With Partially Thick Gate Oxide Film Structure (PTOx-TMOS)

Cited by 8 publications

References 2 publications

Improving the Cell Characteristics Using SiN Liner at Active Edge in 4 Gbits NAND Flash Memories

Improving the Cell Characteristics Using SiN Liner at Active Edge in 4 Gbits NAND Flash Memories

Investigation of correlation between device structures and switching losses of IGBTs

Negative Bias Temperature Stress Reliability in Trench-Gated P-Channel Power MOSFETs

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