High performance and low power FIR filter design based on sharing multiplication

Abstract

We present a high performance and low power FIR filter design, which is based on computation sharing multiplier (CSHM). CSHM specifically targets computation re-use in vector-scalar products and is effectively used in our FIR filter design. Efficient circuit level techniques: a new carry select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. The proposed FIR filter architecture was implemented in 0.25 mm technology. Experimental results on a 10 tap low pass CSHM FIR filter show speed and power improvement of 19% and 17%, respectively, with respect to an FIR filter based on Wallace tree multiplier. KeywordsComputation sharing, FIR filter design, high performance and low power carry select adder, conditional capture flip-flop

Design and verification of an ALU‐based universal FIR filter

“…Several FPGA‐based FIR filter design schemes have been around for years, i.e. direct form design (Chen and Chen, 2007), MAC (Jongsun et al , 2002), DA (Rawski et al , 2005), all of which are hardware‐based design. Typically, these schemes design the FIR filter architectures first, then optimize the hardware architectures.…”