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In this paper, a flexible pyroelectric sensor using PbZr 0?3 Ti 0?7 O 3 PZT/P(VDF-TrFE) materials on the polyimide (PI) flexible printed circuit substrate was reported. The fabrication processes, material electric properties and infrared photoelectric response property of the designed sensor were studied. First, the PZT ceramic powder was annealed at temperatures ranging from 300 to 900uC, and then 0-3 PZT/PVDF-TrFE composites films were produced by casting PZT/PVDF-TrFE suspension onto the flexible PI substrates. The highest pyroelectric coefficient obtained using 700uC annealed PZT particulates was 96 mC m 22 K 21 , which was 20% higher than that of unannealed powders. The PI thermal insulation layer and thermal insulation tanks fabricated by laser microetching have been used to improve the photoelectric response ability of the infrared sensor. The specific detectivity of the sensors was calculated from the voltage responsivity and noise. Detectivity D* of the PZT/P(VDF-TrFE) infrared sensor was 1?17610 8 cm Hz 1/2 W 21 at 138?3 Hz modulation frequency. These results demonstrate that the pyroelectric infrared sensor possesses potential applications in flexible electronics.

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Hierarchy communication channel in transaction-level hardware/software co-emulation system for System-on-a-chip (SOC) verification is proposed in the paper. The hierarchy communication channel consists of physical layer, transport layer, transaction layer and application layer. In the paper, research for the channel focuses on communication protocol for transport layer, hardware and software for physical, transport and transaction layer, respectively. This hierarchy communication channel can enhance verification reliability and efficiency because end-user, transactor implementor, infrastructure implementor is only required to concentrate on the work relevant to their specified layers, i.e. physical and transport layers for infrastructure implementor, application layer for end user, transaction layer for transactor implementor. As a verification example, the hierarchy-based transaction-level verification technique has been applied to verification of a digital audio-specific DSP core for AC-3 decoding.

Logic simulation provides SoC verification with full controllability and observability, but it suffers from very slow simulation speed for complex design. Using hardware emulation such as FPGA can have higher simulation speed. However, it is very hard to debug due to its poor visibility. FPGA-based cosimulation seems to draw a balance, but Design Under Test (OUT) still resides in FPGA and remains hard for debugging. So a run-time RTL debugging methodology for FPGA-assisted verification system is presented. This method provides internal nodes probing on an event-driven cosimulation platform and achieves full observability for OUT. The debugging tools are embedded in HDL simulator using Verilog VPI callback, so signals of testbench and internal nodes of OUT can be observed in a single waveform and updated as simulation runs, making debugging more efficient. The proposed debugging method connects internal nodes directly to a PCI-extended bus, instead of inserting extra scan-chain logic, so the overhead for area is reduced. Our experiment shows that, compared with a similar method in (13], the area overhead for debug logic is reduced by 30-50% and compile time is shortened by 40-70%.

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