High performance and low power FIR filter design based on sharing multiplication

Park, Jongsun; Jeong, Won-Ki; Choo, Hunsoo; Mahmoodi-Meimand, H.; Wang, Yongtao; Roy, K.

doi:10.1109/lpe.2002.146758

Cited by 2 publications

(1 citation statement)

References 6 publications

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“…In (1) parallel generation of partial products was performed using pipelined vedic multiplier. Vector scaling operation technique (7) was proposed to improve the speed of computation with two decomposition approaches. Computation Sharing Multipliers (7) for high speed FIR filter design was proposed and it is observed that 33% improvement in the speed is achieved.…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Karatsuba Vedic Multiplier and Computation Sharing Multiplier in the Adaptive Filter Design

Swaminathan*,

Subramaniyam,

Murugesan

2019

IJITEE

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As real time signals change continuously, adaptive filtering is required for noise cancellation. An adaptive filter is one whose characteristics can be modified by adjusting its parameters according to an optimization algorithm The adaptive filtering operations can be implemented as a sequence of logic operations on a Digital Signal Processing (DSP) chip,Gate Arrays such as FPGA or Application Specific Integrated Circuits. There is always a tradeoff in the parameters area, power and speed in VLSI. This paper provides the implementation of adaptive LMS Filter using different types of multiplier and its analysis for the various parameters. The LMS Filter is designed using conventional array multiplier, Computation Sharing Mutliplier(CSHM) and Karatsuba Vedic Multiplier. The results show 70% reduction in delay and 19% reduction in area on using Karatsuba Vedic Multiplier ofr adaptive filter design.

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Section: Introductionmentioning

confidence: 99%

Performance Analysis of Karatsuba Vedic Multiplier and Computation Sharing Multiplier in the Adaptive Filter Design

Swaminathan*,

Subramaniyam,

Murugesan

2019

IJITEE

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Design and verification of an ALU‐based universal FIR filter

Liao

Ruan

et al. 2010

COMPEL - The International Journal for Computation and Mathematics in Electrical and Electronic Engineering

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PurposeTraditionally, each time a new design for a finite impulse response (FIR) filter is required, a new algorithm has to be developed specially for the FIR filter. Furthermore, corresponding hardware architecture must be designed specially to meet the requirement of the FIR specifications. The purpose of this paper is to propose an arithmetic logic unit (ALU)‐based universal FIR filter suitable for realization in field programmable gate arrays (FPGA), where various FIR filters can be implemented just by programming instructions in the ROM with identical hardware architecture.Design/methodology/approachRather than multiplier‐accumulator‐based architecture for conventional FIR, the proposed ALU architecture implements the FIR functions by using accumulators and shift‐registers controlled by the instructions of ROM. Furthermore, time division multiplexing access (TDMA) technique is employed to reduce the chip size. In addition, the proposed FIR architecture is verified in a SOC hardware and/or software co‐emulation system.FindingsAn ALU‐based universal FIR filter suitable for realization in FPGA is designed and verified in a SOC hardware/software co‐emulation system with example of a 64‐tap FIR filter design.Originality/valueA software‐based design method as well as TDMA scheme for the ALU‐based FIR filter are introduced, making FIR filter architecture universal, programmable, and consuming less FPGA resources.

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High performance and low power FIR filter design based on sharing multiplication

Cited by 2 publications

References 6 publications

Performance Analysis of Karatsuba Vedic Multiplier and Computation Sharing Multiplier in the Adaptive Filter Design

Performance Analysis of Karatsuba Vedic Multiplier and Computation Sharing Multiplier in the Adaptive Filter Design

Design and verification of an ALU‐based universal FIR filter

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