High performance 30 nm bulk CMOS for 65 nm technology node (CMOS5)

Morifuji, E.; Kanda, M.; Yanagiya, N.; Matsuda, Shôichi; Inaba, S.; Okano, K.; Takahashi, Kenji; Nishigori, M.; Tsuno, H.; Yamamoto, Takeshi; Hiyama, K.; Takayanagi, Motowo; Oyamatsu, H.; Yamada, Shigeru; Noguchi, T.; Kakumu, M.

doi:10.1109/iedm.2002.1175924

Cited by 15 publications

(6 citation statements)

References 1 publication

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“…The stress in n-MOSFETs does not increase the v inj as in the p-MOS devices, consequently the stress-induced I ON improvements are larger in p-MOS transistors than in n-MOS ones [78]. [54,56,57,[92][93][94][95][96][97][98][99] Quite interestingly, the simulation prediction of a stressinduced improvement of the I ON disadvantage of pMOSFETs is supported by the experimental data. In fact Fig.…”

Section: Simulation Results For Nano-scale Mosfetsmentioning

confidence: 81%

Semi-classical transport modelling of CMOS transistors with arbitrary crystal orientations and strain engineering

et al. 2009

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This paper reviews the basic methodologies and models used in the semi-classical modelling of CMOS transistors in the framework of the nowadays generalized scaling scenario. The capabilities to describe devices with arbitrary crystal orientations and strain configurations are discussed. Several simulation results are illustrated and compared to the experiments to assess the understanding of the underlying physics and the predictive capabilities of the models. A case study concerning the drain currents in nano-scale uniaxially strained MOSFETs is presented and it shows how the strain engineering may change the traditional on-current disadvantage of the p-MOS compared to the n-MOS transistors.

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Section: Simulation Results For Nano-scale Mosfetsmentioning

confidence: 81%

Semi-classical transport modelling of CMOS transistors with arbitrary crystal orientations and strain engineering

et al. 2009

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“…The amount of impurity diffusion is strongly affected by spike RTA. 11) Therefore, the impurity profiles of in situ doped boron before and after spike RTA are shown for comparison in Fig. 5.…”

Section: Shallow Junction Propertymentioning

confidence: 99%

Planar Metal–Oxide–Semiconductor Field-Effect Transistors with Raised Source and Drain Extensions Fabricated by In situ Boron-Doped Selective Silicon Epitaxy

Kikuchi¹,

Tateshita²,

Miyanami³

et al. 2010

Jpn. J. Appl. Phys.

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Junction depth and parasitic resistance have a trade-off relationship. To improve this relationship, in situ boron-doped selective Si epitaxy was used to fabricate metal–oxide–semiconductor field-effect transistors (MOSFETs) with raised source and drain extensions and a facet. The amount of boron diffusion was small and the MOSFET also had low extension sheet resistance. Furthermore, with the optimization of four process parameters, spike rapid thermal annealing (RTA) temperature, halo dose, impurity concentration introduced by in situ doping, and epitaxial Si thickness, the relationship between the gate length at I off=100 nA/µm and the drive current at I off=100 nA/µm was improved.

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“…The inefficiently scaled spacer width is fixed at 30 nm. 5,15,17) Four values for the gate dielectric or the offset spacer dielectric were used, including those of air (" r ¼ 1), SiO 2 (" r ¼ 3:9), Si 3 N 4 (" r ¼ 7:5), Al 2 O 3 (" r ¼ 9), HfO 2 (" r ¼ 25) and TiO 2 (" r ¼ 80), to study the fringing electric field effect on device performance.…”

Section: Simulation Proceduresmentioning

confidence: 99%

“…Therefore, most of the advanced nanoscale devices reported previously have a large spacer width that is comparable or larger than the gate length. [14][15][16][17][18][19] This leads to the situation in which the fringing electric field becomes a very important factor in short-channel devices because of a hardly scaled offset spacer width. In addition, the wide offset spacer will increase the parasitic series source/drain resist-ance R S/D , resulting in the further degradation of transistor performance.…”

Section: Introductionmentioning

confidence: 99%

Fringing Electric Field Effect on 65-nm-Node Fully Depleted Silicon-on-Insulator Devices

Wen¹,

Chao²,

Kao³

et al. 2006

jjap

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In this study, the fringing electric field effect on 65-nm-node technology fully depleted silicon-on-insulator (FD SOI) device is comprehensively examined. A new anomalous degradation in device on-state/off-state characteristics on a nanoscale metaloxide-semiconductor field-effect transistor (MOSFET) with high-gate dielectrics is reported, the so-called fringing-induced barrier lowering (FIBL). This is due to the decrease in fringing electric field and increase in the gate dielectric thickness when gate dielectric permittivity increased. We observe that FIBL can be effectively suppressed using a stack gate dielectric structure. In addition, we also implement a high-offset spacer to further improve the on-state driving current I on to approximately 26% higher than that of a conventional silicon dioxide offset spacer and reduce the off-state leakage current I off by about 34%. This benefit is due to the enhanced high vertical channel electric field obtained via the offset spacer using a high-material as a spacer. This enhanced fringing electric field can markedly increase I on =I off current ratio and reduce subthreshold swing (S-factor) to improve MOSFET performance, which implies that gate-to-channel controllability can be improved markedly. This would play an important role beyond the 65-nm-node technology.

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High performance 30 nm bulk CMOS for 65 nm technology node (CMOS5)

Cited by 15 publications

References 1 publication

Semi-classical transport modelling of CMOS transistors with arbitrary crystal orientations and strain engineering

Semi-classical transport modelling of CMOS transistors with arbitrary crystal orientations and strain engineering

Planar Metal–Oxide–Semiconductor Field-Effect Transistors with Raised Source and Drain Extensions Fabricated by In situ Boron-Doped Selective Silicon Epitaxy

Fringing Electric Field Effect on 65-nm-Node Fully Depleted Silicon-on-Insulator Devices

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