High performance 0.25 μm SiGe and SiGe:C HBTs using non selective epitaxy

Baudry, H.; Martinet, B.; Fellous, C.; Kermarrec, O.; Campidelli, Y.; Laurens, M.; Marty, M.; Mourier, J.; Troillard, G.; Monroy, A.; Dutartre, D.; Bensahel, D.; Vincent, Gilbert; Chantre, A.

doi:10.1109/bipol.2001.957855

Cited by 28 publications

(10 citation statements)

References 1 publication

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“…To validate the proposed topology and compare its performance with that of a differential pair driven single-ended, we have designed a test IC [15] using the STMicroelectronics BiCMOS7 technology [16], that features SiGe HBT's with a maximum f T in excess of 65 GHz. The IC contains three different test circuits, to allow de-embedding of measurements and comparison: two circuits are singleended to differential converters (S2D) with 50-X input and output buffers, as shown schematically in Fig.…”

Section: Simulations and Measurement Resultsmentioning

confidence: 99%

A wideband high-CMRR single-ended to differential converter

Centurelli

Luzzi

Tommasino

et al. 2008

Analog Integr Circ Sig Process

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A novel circuit topology that provides wideband single-ended to differential conversion is presented. The proposed circuit exploits a negative feedback loop to generate a second input signal for a differential pair, thus obtaining 6 dB extra conversion gain and higher CMRR with respect to a simple differential pair driven singleended. A signal and noise model for the circuit is proposed, based on admittance parameters and the use of a novel analysis technique to open the feedback loop while maintaining closed loop loading effects. The model is exploited to derive design guidelines in bipolar and MOS technologies. Measurements on a test chip in STMicroelectronics BiCMOS7 technology are reported to compare the performance of the proposed topology and of a simple differential pair used as single-ended to differential converter

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Section: Simulations and Measurement Resultsmentioning

confidence: 99%

A wideband high-CMRR single-ended to differential converter

Centurelli

Luzzi

Tommasino

et al. 2008

Analog Integr Circ Sig Process

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“…The first single-chip 10-Gb/s SONET SERDES [14] and a 10-Gb/s Ethernet (10GE) SERDES (Fig. 3) fabricated in 0.35μm [2] and 0.25μm [3] SiGe BiCMOS processes were introduced in December 2000 and the summer of 2001, respectively. Both these ICs rely on simpler ECL families to reduce the supply voltage of the 10-Gb/s circuitry to 3.3V.…”

Section: Sige Hbt and Serdes Performance Scalingmentioning

confidence: 99%

“…Historically, due to larger-scale economies, wireless and (briefly) fibre-optic applications have driven SiGe BiCMOS process development [1]- [3]. While SiGe HBT performance has steadily improved over the last few years [4]- [8], the frequency of most applications has remained in the 2-10 GHz range.…”

Section: Introductionmentioning

confidence: 99%

SiGe BiCMOS for Analog, High-Speed Digital and Millimetre-Wave Applications Beyond 50 GHz

Chalvatzis¹,

Yau²,

Hazneci³

et al. 2006

2006 Bipolar/BiCMOS Circuits and Technology Meeting

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“…A common way of introducing epitaxy in the device process is by non-selective epitaxy followed by a deposition of a dielectric layer, which requires patterning [1,3]. Thus the process becomes non-self-aligned.…”

Section: Introductionmentioning

confidence: 99%

A Self-Aligned Double Poly-Si Process Utilizing Non-Selective Epitaxy of SiGe:C for Intrinsic Base and Poly-SiGe for Extrinsic Base

Pejnefors

Johansson²,

Wittborn³

et al. 2002

32nd European Solid-State Device Research Conference

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A self-aligned double poly-Si process using nonselective epitaxy of SiGe:C for the intrinsic base and a dual stack of poly-Si and poly-SiGe for the extrinsic base is presented. Self-alignment of the extrinsic base is obtained by detailed control of the emitter window etch procedure. The etch of the extrinsic base is endpointed at the poly-Si/poly-SiGe interface, and is followed by a timed etch of the SiGe film. Due to the selectivity towards Si, the etch can be stopped at the epitaxial Si surface.The SiGe:C epitaxy is obtained using ultra-high vacuum chemical vapor deposition (UHV/CVD). As a result of the slightly higher growth rate of the epitaxial film compared to the polycrystalline material, an almost planar surface could be obtained.Working devices have been verified by electrical measurements.

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High performance 0.25 μm SiGe and SiGe:C HBTs using non selective epitaxy

Abstract: A robust 0.25pm double-poly SiGe HBT structure using non selective epitaxy has been developed. The device features 70/90GHz fT/fmx with pure SiGe base in 0.25pm BiCMOS technology. Performances up to 120/100GHz fT/fmax are demonstrated for SiGe:C base transistors.

Cited by 28 publications

References 1 publication

A wideband high-CMRR single-ended to differential converter

A wideband high-CMRR single-ended to differential converter

SiGe BiCMOS for Analog, High-Speed Digital and Millimetre-Wave Applications Beyond 50 GHz

A Self-Aligned Double Poly-Si Process Utilizing Non-Selective Epitaxy of SiGe:C for Intrinsic Base and Poly-SiGe for Extrinsic Base

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