High performance 0.1 μm CMOS devices with 1.5 V power supply

Taur, Yuan; Wind, Shalom J.; Mii, Y. J.; Lii, Y. T.; Moy, D.; Jenkins, K.A.; Chen, C.L.; Coane, P.; Klaus, D.; Bucchignano, J.; Rosenfield, M. G.; Thomson, M. G. R.; Polcari, M.R.

doi:10.1109/iedm.1993.347383

Cited by 68 publications

(13 citation statements)

References 8 publications

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“…For the bulk and PDSOI CMOS in this work, the extracted is about 0.47 V, which is close to the longchannel value extrapolated at maximum transconductance of the linear drain current. 1 This indicates that devices in the ring oscillator have little roll-off. Fig.…”

Section: A Scheme To Compare Delaymentioning

confidence: 96%

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High-performance 0.07-μm CMOS with 9.5-ps gate delay and 150 GHz f/sub T/

Wann

Assaderaghi

Shi

et al. 1997

IEEE Electron Device Lett.

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We report room-temperature 0.07-m CMOS inverter delays of 13.6 ps at 1.5 V and 9.5 ps at 2.5 V for SOI substrate; 16 ps at 1.5 V and 12 ps at 2.5 V for bulk substrate. This is the first room-temperature sub-10 ps inverter ring oscillator delay ever reported. PFET with very high drive current and reduction in parasitic resistances and capacitances for both NFET and PFET, realized by careful thermal budget optimization, contribute to the fast device speed. Moreover, the fast inverter delay was achieved without compromising the device short-channel characteristics. At V dd = 1:5 V and I o 2:5 nA/m, minimum L e is about 0.085 m for NFET and 0.068 m for PFET. PFET Ion is 360 A/m, which is the highest PFET Ion ever reported at comparable V dd and I o . The SOI MOSFET has about one order of magnitude higher I o than bulk MOSFET due to the floating-body effect. At around 0.07 m L e , the NFET cut-off frequencies are 150 GHz for SOI and 135 GHz for bulk. These performance figures suggest that subtenth-micron CMOS is ready for multi-gigahertz digital circuits, and has a good potential for RF and microwave applications. I. DEVICE FABRICATION AND PERFORMANCES UB-TENTH-MICRON CMOS continues to deliver higher performance and less power consumption at lower . In this work sub-tenth-micron CMOS devices and circuits were fabricated on bulk and SOI substrates. The device fabrication processes were similar to that in [1]. The gate level was patterned using X-ray lithography, enabling high resolution and high throughput. Functional DC-to-DC converters, 10-GHz voltage-controlled oscillators, 5.8-GHz low-noise amplifiers, and 6-GHz frequency dividers were also successfully fabricated. The oxide thickness was 27Å as measured by an ellipsometer.CMOS inverter ring oscillators had delays of 16 ps at 1.5 V, 13.5 ps at 1.8 V, and 12 ps at 2.5 V for bulk substrate; 13.6 ps at 1.5 V, 11 ps at 1.8 V, and 9.5 ps at 2.5 V for SOI substrate, as seen in Fig. 1. This is the first room-temperature sub-10 ps CMOS ring oscillator delay reported. The partiallydepleted (PD) SOI CMOS devices (140 nm starting silicon thickness) in general have improved the inverter delay by about 25%, although is one order of magnitude higher due to the floating-body effect. This fast ring oscillator speed mainly resulted from the high performance PFET and the reduction of the parasitic resistances and capacitances of the short-channel devices, both were realized by reducing the Manuscript received September 11, 1997. This work was supported in part by NCCOSC under Contract N66001-93-C-6005.The authors are with IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA.Publisher Item Identifier S 0741-3106(97)09099-X. Fig. 1. Inverter ring oscillator delays for bulk, PDSOI, and FDSOI MOS-FET's in this work, together with published data [1]-[4]. The models are detailed in Fig. 4. thermal budget. Shallow source and drain extensions with abrupt profiles in both the vertical and the lateral directions are the keys to simultaneously reduce overlap capacitances and series...

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Section: A Scheme To Compare Delaymentioning

confidence: 96%

“…In this work sub-tenth-micron CMOS devices and circuits were fabricated on bulk and SOI substrates. The device fabrication processes were similar to that in [1]. The gate level was patterned using X-ray lithography, enabling high resolution and high throughput.…”

Section: Device Fabrication and Performancementioning

confidence: 99%

High-performance 0.07-μm CMOS with 9.5-ps gate delay and 150 GHz f/sub T/

Wann

Assaderaghi

Shi

et al. 1997

IEEE Electron Device Lett.

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“…Indium was recommended for fabricating steep retrograde channel profiles due to the heavy ion atom and the strong segregation to oxide [1]- [3], and shallow source-drain extensions with pre-amorphization for the dechanneling [4], [5]. For indium pocket profiling, two approaches, that is, low-dose tilted ion implantation [6] and high-dose ion implantation [7], have been explored.…”

Section: Introductionmentioning

confidence: 99%

Double pocket architecture using indium and boron for sub-100 nm MOSFETs

Odanaka

Hiroki

Yamashita

et al. 2001

IEEE Electron Device Lett.

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A double pocket architecture for sub-100 nm MOSFET's is proposed on the basis of indium pocket profiling at higher dose than the amorphization threshold. At high dose, the low-energy indium pockets realize the improvement of short channel effects and shallow extension formation of highly doped drain, maintaining the low junction leakage level. Double pocket architecture using indium and boron is demonstrated in a 70 nm gate length MOSFET with high drive currents and good control of the short channel effects.

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“…Due to the confinement of their motion in the direction normal to the surface, electrons in the inversion layer must be treated quantum mechanically as a two-dimensional electron gas (2-DEG) rather than classically as a three-dimensional (3-D) gas [12]. The gate leakage current increases exponentially with decreasing oxide thickness.…”

Section: Gate Oxidementioning

confidence: 99%