High-linearity continuous-time filter in 5-V VLSI CMOS

An analog CMOS low-pass Active-Gm-RC biquadratic cell is presented. The cell combines the advantage of GM-C filters (no parasitic poles) with the advantages of Active-RC filter (large linear range). Two additional digital-based circuits allow to control the pole frequency and to reduce the effects of the non-dominant poles. A 4th order low-pass Butterworth filter with a 2.11 MHz cut-off frequency and a DC-gain of 32 dB for UMTS receiver has been designed in a 0.18 µm CMOS technology with 1.8 V supply voltage. The filter exhibits a −93 dBV input-referred noise with a power consumption of 2.16 mW while the linearity performances corresponds to an in-band IIP3 of 4 dBm and an out-of-band IIP3 of 35 dBm. An Active Gm-RC band-pass cell is presented as possible alternative application.

show abstract

“…(2 N −1). For a technological spread of ξ % the design equations are: This array has a maximum quantization error [17] approximately given by:…”

Section: Filter Frequency Response Alignmentmentioning

confidence: 99%

Active-Gm-RC Continuous-Time Biquadratic Cells

D'Amico

Basçhirotto

2005

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…For low-voltage compatibility, a possible solution is to use programmable arrays of polysilicon resistors and/or capacitors [1,2]. A −76 dB THD and a dynamic range better than 81.5 dB are achieved with this approach.…”

Section: Introductionmentioning

confidence: 99%

Using MOS current dividers for linearization of programmable gain amplifiers

Sanz

Celma

Calvo

2007

Circuit Theory & Apps

View full text Add to dashboard Cite

Two highly linear, digitally programmable gain amplifiers are presented and compared in terms of linearity, frequency, area and power consumption. High linearity and wide gain tuning range with moderate area consumption are the main benefits of both configurations. Furthermore, constant bandwidth is achieved by means of switched compensation capacitor arrays. Three-bit prototypes were integrated in a 0.35 m-3.3 V CMOS process with 2.5 V supply voltage. Experimental distortion levels are better than −68 dB for 1 MHz and 1 V p-p output signals in both configurations; hence, the suitability of the linearization technique based on MOS current dividers is shown.

show abstract

“…The first indirect automatic tuning scheme was described by Canning and Wilson in a 1976 patent, and currently, many well-known implementations have used indirect tuning methods [3,6,8,10]. Figure 1 shows the practical scheme of a master-slave auto-tuning system highlighting the required control blocks for frequency and quality factor (Q).…”

Section: Indirect Tuning Schemementioning

confidence: 99%

“…One possibility is the dual-slope calibrator considered in [10] where the response accuracy is automatically tuned to a mean value of within ±5% for three different CT filters. Digital tunability is provided by constructing each capacitor with an array of binary-weighted capacitors, switched in or out under the control of the digital word.…”

Section: Digital Frequency Tuning Schemementioning

confidence: 99%

Continuous‐time filter featuring Q and frequency on‐chip automatic tuning

Otín

Celma

Aldea

2009

Circuit Theory & Apps

View full text Add to dashboard Cite

SUMMARYThe on-chip automatic tuning of digitally programmable continuous-time G m -C filters with a wide operation range employing a hybrid analog-digital master-slave scheme is reported in this work. The master system is implemented with a voltage-controlled filter (VCF) with the same programmable transconductance cells as the main filter to enhance the matching between master and slave. The frequency tuning method, for both analog and digital control, is based on a digital phase comparator included in the phase-locked loop achieving high-precision tunability. The digital frequency tuning is obtained with an error of ±4% and the maximum settling time when changing between two consecutive digital words is 0.3 s. Once the digital word is fixed, the analog tuning finely adjusts the value of the characteristic frequency to the reference and corrects for possible temperature variations with a settling time of 0.2 s. The analog frequency control covers the whole discrete step with a maximum error of ±5%. Furthermore, a magnitude-locked loop (MLL) Q-tuning block is simultaneously applied to the system in order to precisely control the quality factor of the G m -C filter by using an appropriate envelope detector. According to the obtained results, both post-layout simulation and experimental results, the adopted scheme has resulted as a useful and adequate solution to implement the complete auto-tuning system of digitally programmable continuous-time filters, including frequency and Q-control.

show abstract

High-linearity continuous-time filter in 5-V VLSI CMOS

Cited by 93 publications

References 13 publications

Active-Gm-RC Continuous-Time Biquadratic Cells

Active-Gm-RC Continuous-Time Biquadratic Cells

Using MOS current dividers for linearization of programmable gain amplifiers

Continuous‐time filter featuring Q and frequency on‐chip automatic tuning

Contact Info

Product

Resources

About