High-level synthesis with behavioral level multi-cycle path analysis

Zheng, Hao; Gurumani, Swathi; Yang, Liwei; Chen, Deming; Rupnow, Kyle

doi:10.1109/fpl.2013.6645541

Cited by 16 publications

(11 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…HW Implementation: Workload analysis together with modeling determines a chosen set of CPU customizations; however, during implementation, it is critical that automation can assist in implementing the low level details so that area, performance, and power estimates can be achieved or improved on. High-level synthesis [32,33] and automated IP-and system-integration [34] can fill an important role in performing detailed implementation. Many integration details are complex yet tedious and error prone.…”

Section: Modelingmentioning

confidence: 99%

“…These options improve performance and power consumption, but IoT applications must balance power, performance, size, and cost through the use of embedded GPUs [6,7,8,9,10] and FPGA-based SoCs [11,12], which can achieve even better energy efficiency [13,14,15]. Recent advances in high-level synthesis [16,17,18,19,20,21] have improved the ease of FPGA programming, which simplifies use of FPGAs in IoT applications.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs

Chen

Cong

Gurumani

et al. 2016

IET cyber-phys. syst.

Self Cite

View full text Add to dashboard Cite

The rise of the Internet of Things has led to an explosion of new sensor computing platforms. The complexity and application domains of IoT devices range from simple self-monitoring devices in vending machines to complex interactive devices with artificial intelligence in smart vehicles and drones. As IoT developers wish to meet more aggressive platform objectives and protect market share through feature differentiation, they must choose between low-cost, and lowperformance CPU-based commercial-off-the-shelf (COTS) systems, and high-performance custom platforms with hardware accelerators such as GPU and FPGA. Both COTS and custom platform designs introduce a variety of design challenges-the extreme pressures on time-to-market, design cost, and development risk are also driving a voracious demand for new CAD technologies to enable rapid, low cost design of effective IoT platforms with smaller design teams and lower risk. In this article, we present a generic IoT device design flow and discuss platform choices available for IoT devices to efficiently tradeoff cost, power, performance and volume constraints: CPUbased systems, and custom platforms that contain hardware accelerators such as FPGA and embedded GPUs. We demonstrate this design process through a driving application in computer vision. We also present current critical design automation needs for IoT development and demonstrate how our prior work in CAD for FPGAs and SoCs begin to address these needs.

show abstract

Section: Modelingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs

Chen

Cong

Gurumani

et al. 2016

IET cyber-phys. syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…As we will show in Section VII, the ability to detect all multicycle paths alone already helps logic synthesis to improve the hardware quality. In addition, we also present two optimizations based on BL-MCPA, including schedule-independent chaining (Section V) and MUX pipelining (Section VI), which are not presented in our prior conference publication [24].…”

Section: Related Workmentioning

confidence: 99%

High-Level Synthesis With Behavioral-Level Multicycle Path Analysis

Zheng

Gurumani²,

Yang

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

High-level synthesis (HLS) tools generate registertransfer level (RTL) hardware descriptions from behaviorallevel specifications through resource allocation, scheduling and binding. Traditionally, HLS tools build datapath pipelines by inserting pipeline registers to break combinational logic into single-cycle segments; accurately analyzing that the number of available cycles for signal propagation is proven to be infeasible at the RT-level. Thus, RT-level timing analyses must pessimistically assume each path has at most one cycle for signal propagation. This leads to false positives in critical-path analyses, prevents RTL synthesis tools from optimizing real critical paths, and forces HLS flows to insert pipeline registers without improving hardware quality. In this paper, we present an efficient behavioral-level multicycle path analysis (BL-MCPA) algorithm that leverages control-data flow information to reduce time complexity of multicycle path analysis from exponential to polynomial. BL-MCPA helps eliminate false positives in timing analysis, and improves the reported f max by 15% on average. With BL-MCPA, we avoid unnecessary pipeline register insertion, and reduce execution latency by 25% and register usage by 29% under a user f max constraint of 300 MHz. Using BL-MCPA, we replace large multiplexers (MUXs) by pipelined MUX-trees and reduce execution latency of hardware by up to 67% on designs whose performance is limited by the large MUXs.

show abstract

“…Automatically identifying multi-cycle paths are at RTL are well studied in [6], [7], [8], [10]. MCP is even studied recently in C based high-level synthesis as well in [9]. However, MCP is not supported yet in any model based high-level synthesis tool.…”

Section: Introductionmentioning

confidence: 96%

On multi-cycle path support in model based high-level synthesis

Karfa¹,

Jain²

2014

Proceedings of the 2014 IEEE Students' Technology Symposium

View full text Add to dashboard Cite

Multi-cycle paths (MCPs) are commonly used by designers as an efficient way to relax the timing constraints on eligible paths in their designs. MCP directs synthesis tools to relax the optimization on the specified paths. The MCP constraints are widely used in the Register Transfer Level (RTL) designs and are propagated to downstream tools. With the evolution of high level synthesis (HLS) tools, design entry and the constraints have to be specified at a higher level of abstraction. In addition, majority of the HLS users are system level designs or DSP experts who have little knowledge of RTL implementation flows. Hence, it is important for HLS tools to provide a methodology for specifying MCP constraints at a higher level of abstraction, consider the MCP paths during HLS and also forward annotate the MCP constraints to the RTL implementation tools. In this paper, we have created such a methodology for Synopsys Synphony model compiler (SMC), a model based HLS tool. To the best of our knowledge, MCP is supported for the first time in model based HLS flow. The effectiveness of specifying MCP on higher abstraction level is demonstrated on sample example designs.

show abstract

High-level synthesis with behavioral level multi-cycle path analysis

Cited by 16 publications

References 23 publications

Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs

Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs

High-Level Synthesis With Behavioral-Level Multicycle Path Analysis

On multi-cycle path support in model based high-level synthesis

Contact Info

Product

Resources

About