High-Level Synthesis With Behavioral-Level Multicycle Path Analysis

Abstract

High-level synthesis (HLS) tools generate registertransfer level (RTL) hardware descriptions from behaviorallevel specifications through resource allocation, scheduling and binding. Traditionally, HLS tools build datapath pipelines by inserting pipeline registers to break combinational logic into single-cycle segments; accurately analyzing that the number of available cycles for signal propagation is proven to be infeasible at the RT-level. Thus, RT-level timing analyses must pessimistically assume each path has at most one cycle for signal propagation. This leads to false positives in critical-path analyses, prevents RTL synthesis tools from optimizing real critical paths, and forces HLS flows to insert pipeline registers without improving hardware quality. In this paper, we present an efficient behavioral-level multicycle path analysis (BL-MCPA) algorithm that leverages control-data flow information to reduce time complexity of multicycle path analysis from exponential to polynomial. BL-MCPA helps eliminate false positives in timing analysis, and improves the reported f max by 15% on average. With BL-MCPA, we avoid unnecessary pipeline register insertion, and reduce execution latency by 25% and register usage by 29% under a user f max constraint of 300 MHz. Using BL-MCPA, we replace large multiplexers (MUXs) by pipelined MUX-trees and reduce execution latency of hardware by up to 67% on designs whose performance is limited by the large MUXs.

Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs

“…HW Implementation: Workload analysis together with modeling determines a chosen set of CPU customizations; however, during implementation, it is critical that automation can assist in implementing the low level details so that area, performance, and power estimates can be achieved or improved on. High-level synthesis [32,33] and automated IP-and system-integration [34] can fill an important role in performing detailed implementation. Many integration details are complex yet tedious and error prone.…”

“…Design automation for SoC implementation phase is possible by using HLS techniques that enable automated translation of high-level language descriptions such as C/C++, SystemC and CUDA to RTL [32,33,14] and/or by automated integration of several IP blocks including register transfer level (RTL) blocks.…”

JIT trace-based verification for high-level synthesis

“…Our JIT trace-based verification framework is built on VAST HLS, an existing LLVM-based HLS framework [9], [10]. VAST HLS translates C/C++ source inputs to Verilog RTL implementation by following typical HLS steps such as parsing, compiler optimization, allocation, scheduling, binding and RTL code generation.…”