High-Level Synthesis through metaheuristics and LUTs optimization in FPGA devices

Bulnes, Darian Reyes Fernández de; Simental, Juan Carlos Dibene; Maldonado, Yazmin; Trujillo, Leonardo

doi:10.3233/aic-170727

Cited by 2 publications

(1 citation statement)

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“…It helps to make a good decision in making investments by considering multiple objectives (profit, risk, etc.) [ 34 ], contributes to efficient management of resources (e.g., water) in distribution systems [ 35 ], improves communication systems in terms of average latency and average power consumption [ 36 ], reduces the amount of resources used in Field Programmable Gate Array (FPGA) devices [ 37 ] in the logic synthesis stage [ 38 ], and the examples can go on.…”

Section: Methodsmentioning

confidence: 99%

Cost-Efficient Approaches for Fulfillment of Functional Coverage during Verification of Digital Designs

2022

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Digital integrated circuits play an important role in the development of new information technologies and support Industry 4.0 from a hardware point of view. There is great pressure on electronics companies to reduce the time-to-market for product development as much as possible. The most time-consuming stage in hardware development is functional verification. As a result, many industry and academic stakeholders are investing in automating this crucial step in electronics production. The present work aims to automate the functional verification process by means of genetic algorithms that are used for generating the relevant input stimuli for full simulation of digital design behavior. Two important aspects are pursued throughout the current work: the implementation of genetic algorithms must be time-worthy compared to the application of the classical constrained-driven generation and the verification process must be implemented using tools accessible to a wide range of practitioners. It is demonstrated that for complex designs, functional verification powered by the use of genetic algorithms can go beyond the classical method of performing verification, which is based on constrained-random stimulus generation. The currently proposed methods were able to generate several sets of highly performing stimuli compared to the constraint-random stimulus generation method, in a ratio ranging from 57:1 to 205:1. The performance of the proposed approaches is comparable to that of the well-known NSGA-II and SPEA2 algorithms.

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Section: Methodsmentioning

confidence: 99%

Cost-Efficient Approaches for Fulfillment of Functional Coverage during Verification of Digital Designs

2022

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Development of Multiobjective High-Level Synthesis for FPGAs

Bulnes

Maldonado

Trujillo

2020

Scientific Programming

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Traditionally, the High-Level Synthesis (HLS) for Field Programmable Gate Array (FPGA) devices is a methodology that transforms a behavioral description, as the timing-independent specification, to an abstraction level that is synthesizable, like the Register Transfer Level. This process can be performed under a framework that is known as Design Space Exploration (DSE), which helps to determine the best design by addressing scheduling, allocation, and binding problems, all three of which are NP-hard problems. In this manner, and due to the increased complexity of modern digital circuit designs and concerns regarding the capacity of the FPGAs, designers are proposing novel HLS techniques capable of performing automatic optimization. HLS has several conflicting metrics or objective functions, such as delay, area, power, wire length, digital noise, reliability, and security. For this reason, it is suitable to apply Multiobjective Optimization Algorithms (MOAs), which can handle the different trade-offs among the objective functions. During the last two decades, several MOAs have been applied to solve this problem. This paper introduces a comprehensive analysis of different MOAs that are suitable to perform HLS for FPGA devices. We highlight significant aspects of MOAs, namely, optimization methods, intermediate structures where the optimizations are performed, HLS techniques that are addressed, and benchmarks and performance assessments employed for experimentation. In addition, we show the analysis of how multiple objectives are optimized currently in the algorithms and which are the objective functions that are optimized. Finally, we provide insights and suggestions to contribute to the solution of major research challenges in this area.

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High-Level Synthesis through metaheuristics and LUTs optimization in FPGA devices

Cited by 2 publications

References 20 publications

Cost-Efficient Approaches for Fulfillment of Functional Coverage during Verification of Digital Designs

Cost-Efficient Approaches for Fulfillment of Functional Coverage during Verification of Digital Designs

Development of Multiobjective High-Level Synthesis for FPGAs

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