High-Level Dataflow Transformations Using Taylor Expansion Diagrams

Ciesielski, Maciej; Guillot, J.; Gomez-Prado, D.; Boutillon, Emmanuel

doi:10.1109/mdt.2009.82

Cited by 3 publications

(1 citation statement)

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“…TDS offers a systematic way to transform the initial specification, written in C or C++, into a DFG that addresses the constraints of hardware implementation and explores a larger space of architectural solutions. Its applications to high-level synthesis can be found in [6,7,5]. TED is a compact, graph-based data structure that provides an efficient way to represent word-level computation in a canonical, factored form.…”

Section: Previous Workmentioning

confidence: 99%

Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams

Gomez-Prado

Kim

Ciesielski

et al. 2010

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)

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This paper describes an extension to the Taylor Expansion Diagrams (TED), called Timed TEDs, which makes it possible to represent sequential arithmetic datapaths. Timed TEDs enable register and clock period minimization while performing factorizations and common sub expression eliminations in the data flow graph (DFG). Specifically, timed TEDs allow a wider range of retiming options as the computations in the DFG can be modified while performing retiming. In this paper we discuss the formalism of timed TEDs and the restrictions it imposes on the TED variable ordering.

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Section: Previous Workmentioning

confidence: 99%