High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs

Enzler, Rolf; Jeger, Tobias; Cottet, Didier; Tröster, Gerhard

doi:10.1007/3-540-44614-1_57

Cited by 54 publications

(50 citation statements)

References 5 publications

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“…The common method used for resource estimation consists of identifying the basic operations in the algorithm, which can be represented as a data flow graph [4] or an RTL netlist [5]. A library of operators characterizing the device is then used to estimate the resources needed by the algorithm.…”

Section: A Resource and Performance Estimationsmentioning

confidence: 99%

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Mapping Loop Structures Onto Parametrized Hardware Pipelines

Masle

Luk

2014

IEEE Trans. VLSI Syst.

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Abstract-This paper shows how a general form of algorithms consisting of a loop with loop dependencies carried from one iteration to the next can automatically be mapped to a parametric hardware design with pipelining and replication features. A technology-independent parametric model of the proposed design is developed to capture the variations of area and throughput with the number of pipeline stages and replications. Our model allows rapid optimization of design parameters by a few pre-synthesis operations. We present an optimization method based on the model. Our method is evaluated using three different applications implemented on a Xilinx Spartan 6 XC6SLX45T FPGA: a carry-save adder-based Montgomery multiplier, a modular exponentiation module, and an integer square root module. Our model facilitates design space exploration; it can quickly predict the area taken by our designs with less than 5% of error, and their maximum frequencies and throughputs with less than 22% of error. Our optimization method is up to 96 times faster than a full search through the design space.Index Terms-Design space exploration, field-programmable gate array (FPGA), hardware mapping, loop-carried dependencies, resource estimation.

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Section: A Resource and Performance Estimationsmentioning

confidence: 99%

“…Therefore, we need a model of the design that facilitates estimating its parameters under speed and area constraints. Such area and speed estimation models are often applicationdependent [1], [3] or technology-dependent [4], [5].…”

Section: Introductionmentioning

confidence: 99%

Mapping Loop Structures Onto Parametrized Hardware Pipelines

Masle

Luk

2014

IEEE Trans. VLSI Syst.

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“…Several methods have been proposed in the past few years for design space exploration of reconfigurable architectures [4][5][6]. However, these methods are either too technologydependent or too architecture-dependent.…”

Section: Related Workmentioning

confidence: 99%

Design space exploration for low-power reconfigurable fabrics

Mehta¹,

Hoare²,

Stander³

et al. 2006

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

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Abstract-This paper presents a parameterizable, coarsegrained, reconfigurable fabric model that attempts to maintain Field Programmable Gate Array (FPGA)-like programmability and Computer Aided Design (CAD), with Application Specific Integrated Circuit (ASIC)-like power characteristics for Digital Signal Processing (DSP) style applications. Using this model, architectural design space decisions are explored in order to define an energy-efficient fabric. The impact on energy and performance due to the variation of different parameters such as datawidth and interconnection flexibility has been studied. The multiplexer cardinality usage has also been studied by mapping some of the signal processing applications onto the fabric. The results point to the use of power optimized 32-bit width computational elements interconnected by low cardinality multiplexers like 4:1 multiplexers.

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“…Estimating the run time of a hardware implementation on an FPGA is achieved in [6] by simulating the algorithm and using a performance model of the FPGA. Also performance estimations for FPGAs are shown in [7]. In [8] reliable estimation of the execution time of an algorithm implemented in software running on a processor is presented.…”

Section: Related Workmentioning

confidence: 99%

Static Estimation of Execution Times for Hardware Accelerators in System-on-Chips

Hölzer

Rupp

2005

2005 International Symposium on System-on-Chip

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Abstract-Early performance estimation of a System-on-Chip design is a key issue for a successful design methodology. One of the most important parameters is the run time of a function. Especially optimization techniques like hw/sw partitioning rely on those estimations. This paper presents a static analysis method in order to characterize a hardware acceleration unit regarding its run time. The performance of the presented method is shown on several examples from the embedded systems area and compared to results from high level synthesis.

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High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs

Cited by 54 publications

References 5 publications

Mapping Loop Structures Onto Parametrized Hardware Pipelines

Mapping Loop Structures Onto Parametrized Hardware Pipelines

Design space exploration for low-power reconfigurable fabrics

Static Estimation of Execution Times for Hardware Accelerators in System-on-Chips

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