High-Hole-Mobility Silicon Germanium on Insulator Substrates with High Crystalline Quality Obtained by the Germanium Condensation Technique

Abstract

Thin SiGe-on-insulator (SGOI) substrates with Ge content varying between 42 and 93% were produced by the Ge condensation technique and full structural characterization was carried out. In a second step, the electrical properties of these substrates were analyzed by the pseudo metal-oxide semiconductor field-effect transistor technique which allowed determination of the carrier low-field mobilities, as well as the density of fixed charges in the buried oxide (BOX) and the density of interface traps at the BOX-SiGe film interface. Optimization of intermediate anneals in argon during the condensation process made the production of high crystalline quality and high-mobility substrates possible (up to 400cm2normalV−1normals−1 for a 93% SGOI). Opposite trends were observed for holes and electrons: while the hole mobility increases with increasing Ge content, the electron mobility decreases. In addition, the density of interface traps and also the density of oxide charges were found to increase with increasing Ge content. Possible causes for this increase are discussed.

Effective passivation of defects in Ge-rich SiGe-on-insulator substrates by Al2O3 deposition and subsequent post-annealing

“…However, with an increase in Ge%, I off drastically increases for as-fabricated SGOI's. This phenomena have been observed by other group and our previous work [5,10]. When Ge% increases to 90%, the I on/off ratio decreases to less than 10 4 .…”

“…Furthermore, these electrically active defects act as acceptors, which cause a hole concentration (N p ) and acceptor concentration (N A ) as high as 10 16 -10 18 cm À3 in Ge-rich SGOI [8,9]. As a result, a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) on Ge-rich SGOI exhibits a large off current (I off ) and is difficult to operate in full depletion (FD) mode [5,10]. nMOSFET on Ge-rich SGOI exhibits a high threshold voltage (V T ) [8].…”

“…nMOSFET on Ge-rich SGOI exhibits a high threshold voltage (V T ) [8]. Efforts thus far with post-gas annealing, such as with H 2 and N 2 , as well as optimization of the Ge condensation process, have had limited effects on passivation for these defects [6,10,11]. Therefore, it is still a big challenge to passivate these defects and improve the electrical properties of Ge-rich SGOI.…”

Smooth and high quality epitaxial strained Ge grown on SiGe strain relaxed buffers with 70–85% Ge

“…This is illustrated in Fig. 7, which shows a defective strained Ge layer grown on top of a SiGe-onoxide wafer, fabricated by the classical condensation technique [24]. With an RMS value around 1 nm, the surface roughness of the relaxed SiGe is much higher compared to our CMP-ed strain relaxed buffers.…”

Challenges and opportunities in advanced Ge pMOSFETs

“…One is the high acceptor concentration which is typically observed [109][110][111][112]. This problem also exists for GeOI wafers fabricated by the transfer of thick Ge epitaxial layers [54,113] and gives rise to large back-channel conduction in pMOSFETs, fabricated in such material.…”