High-gain lateral p-n-p bipolar action in a p-MOSFET structure

Verdonckt-Vandebroek, S.; You, Jaehee; Woo, J.C.S.; Wong, S.S.

doi:10.1109/55.145068

Cited by 23 publications

(6 citation statements)

References 3 publications

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“…In such cases, care must be taken to avoid latch up. Further, in regard to both (i) and (ii), as the fabrication becomes finer, the base (gate) current can be kept lower and a current gain of up to 1000 can be realized easily [2]. Therefore, both problems could be minimized with proper design.…”

Section: Discussionmentioning

confidence: 99%

The BETA‐MOSFET: A novel high‐performance transistor

Yoh

Koizumi

Hashimoto

et al. 1996

Electron Comm Jpn Pt II

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The bipolar enhanced transistor action (BETA)-MOSFET, operating in a mixture of FET mode and bipolar mode, has been fabricated. Unlike the lateral bipolar transistor, its base current can be automatically controlled by the gate voltage. Hence, the device operating voltage can be in a wide range and is a maximum of -4 V. It is confirmed that the device can be treated as a high-performance MOS-FET in circuit analysis. Thee types of device structures, with a gate-substrate contact that includes an ultrathin-film tunnel junction, are fabricated and evaluated. In the p-channel BETA-MOSFET, the drain current and the maximum transconductance are about four times those of the conventional MOSFET while maintaining the same threshold voltage. This result implies that the BETA-MOSFET with a gate length of 1.3 pm exhibits a superior performance equivalent to a 0.1-pm p-MOSFET. 0 1997 Scripta Technica, Inc. Electron Comm Jpn Pt 2,79(12): [47][48][49][50][51][52][53] 1996

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Section: Discussionmentioning

confidence: 99%

The BETA‐MOSFET: A novel high‐performance transistor

Yoh

Koizumi

Hashimoto

et al. 1996

Electron Comm Jpn Pt II

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“…2. Although a similar configuration was proposed before by Colinge [3] and later in [4]- [6], all the authors tried to exploit the extra current produced by the lateral bipolar transistor. This requires the body voltage to be 0.6 V or larger.…”

Section: A Theory Of Operationmentioning

confidence: 99%

“…be also much less than a bulk DTMOSFET. In [3]- [6], the increase of drain current over standard MOSFET at low gate voltages was interpreted as contribution of the lateral bipolar transistor with current gains as high as 10 . As we will show below, a better explanation is the reduction of MOS threshold voltage because of forward body bias.…”

Section: A Theory Of Operationmentioning

confidence: 99%

“…6). Obviously, the net result of threshold voltage reduction is the increase of inversion charge or equivalently the gate capacitance (6) This is demonstrated in Fig. 7, where and of DTMOS and standard MOSFET are compared.…”

Section: A Theory Of Operationmentioning

confidence: 99%

“…Consequently, exploiting the bipolar current might not be practical, as a sizable collector current would require V. The ratio of the drain current to the body (base) current of Fig. 5 can be interpreted as bipolar current gain, and hence the device would have a large current gain [3]- [6]. We believe a more precise interpretation is the threshold voltage reduction by means of forward body bias outlined above.…”

Section: A Theory Of Operationmentioning

confidence: 99%

See 2 more Smart Citations

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

Assaderaghi

Sinitsky

Parke

et al. 1997

IEEE Trans. Electron Devices

370

162

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In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (Vt) drops resulting in a much higher current drive than standard MOSFET for low-power supply voltages. On the other hand, Vt is high at Vgs = 0, therefore the leakage current is low. We provide extensive experimental results and two-dimensional (2-D) device and mixed-mode simulations to analyze this device and compare its performance with a standard MOSFET. These results verify excellent inverter dc characteristics down to V dd = 0:2 V, and good ring oscillator performance down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS). engineering from the Massachusetts Institute of Technology, Cambridge, in 1975, and the M.S.

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Empirical modeling for gate-controlled collector current of lateral bipolar transistors in an n-MOSFET structure

Huang

Chen

1995

Solid-State Electronics

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High-gain lateral p-n-p bipolar action in a p-MOSFET structure

Cited by 23 publications

References 3 publications

The BETA‐MOSFET: A novel high‐performance transistor

The BETA‐MOSFET: A novel high‐performance transistor

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

Empirical modeling for gate-controlled collector current of lateral bipolar transistors in an n-MOSFET structure

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