2011
DOI: 10.1002/pssc.201100249
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High frequency vertical InAs nanowire MOSFETs integrated on Si substrates

Abstract: RF and DC characterization of vertical InAs nanowire MOSFET on Si substrates are presented. Nanowire arrays are epitaxially integrated on Si substrates by use of a thin InAs buffer layer. For device fabrication, high‐k HfO2 gate dielectric and wrap‐gates are used. Post‐deposition annealing of the high‐k is evaluated by comparing one annealed and one not‐annealed sample. The annealed sample show better DC characteristics in terms of transconductance, gm = 155 mS/mm, and on‐current, Ion = 550 mA/mm. Box plots of… Show more

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Cited by 1 publication
(2 citation statements)
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“…The largest on-off ratio of the present VGAA FETs before annealing is similar to that in Lund's study with self-aligned gate structure (4 orders of magnitudes in [18]), but is much larger than that in their devices with normal GAA structure (on-off ratio is 50 before annealing in [27]). After annealing, the present devices show the on-off ratio similar to Lund's devices after annealing, which also reduced dramatically to about 2.5 when the diameter of the NW is 35 nm [27]. The reduced on-off ratio after annealing in our study can be attributed to the improved contact properties and the large diameter of InAs NWs.…”
Section: The Properties Of the Vgaa Nw Fets After Annealingsupporting
confidence: 78%
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“…The largest on-off ratio of the present VGAA FETs before annealing is similar to that in Lund's study with self-aligned gate structure (4 orders of magnitudes in [18]), but is much larger than that in their devices with normal GAA structure (on-off ratio is 50 before annealing in [27]). After annealing, the present devices show the on-off ratio similar to Lund's devices after annealing, which also reduced dramatically to about 2.5 when the diameter of the NW is 35 nm [27]. The reduced on-off ratio after annealing in our study can be attributed to the improved contact properties and the large diameter of InAs NWs.…”
Section: The Properties Of the Vgaa Nw Fets After Annealingsupporting
confidence: 78%
“…The highest drain current of our VGAA NW FETs before annealing (37 µA/µm, V d =+0.5 V, V g = +3.0 V) is obviously smaller than that reported by Lund's group (about 450 mA/mm when [6], and 149 mA/mm when [27]). The smaller on-state current of the present VGAA NW FETs could be due to the following reasons.…”
Section: The Properties Of the Vgaa Nw Fets After Annealingcontrasting
confidence: 75%