2011
DOI: 10.1109/tcpmt.2010.2101890
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High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)

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Cited by 394 publications
(2 citation statements)
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“…45,39 In the following, we discuss the signal integrity consequences of the RDL corrosion on the capacitance-dominated TSV enabled interconnects structures. 46 The Figure 13 pattern eye diagram of (A) calibration substrate, (B) "as received" to (C) highly resistive DUT after EM test (6 days under 100 mA at 290 • C stress). In the unstressed test devices, time domain 10-Gbps pseudorandom bit sequence (PRBS) can be propagated without significant distortion.…”
Section: Resultsmentioning
confidence: 99%
“…45,39 In the following, we discuss the signal integrity consequences of the RDL corrosion on the capacitance-dominated TSV enabled interconnects structures. 46 The Figure 13 pattern eye diagram of (A) calibration substrate, (B) "as received" to (C) highly resistive DUT after EM test (6 days under 100 mA at 290 • C stress). In the unstressed test devices, time domain 10-Gbps pseudorandom bit sequence (PRBS) can be propagated without significant distortion.…”
Section: Resultsmentioning
confidence: 99%
“…The changes in the DUT failure rate with thermal cycling is similar of the in-service changes in characteristic product failure distribution, and are similar to effects of postprocessing anneals and product burn-in. For the devices studied in this work, the chemical transformations are more related to changes in the dielectric than to the metal fill, as TSV RF characteristics at low frequency (< 1 GHz), have been shown to be dictated by the capacitance if the isolation liner (17).…”
Section: Discussionmentioning
confidence: 99%