High Frequency Operation of SuperJunction MOSFET enhanced with Kelvin Source Pin

Cacciato, M.; Rizzo, Santi Agatino; Scarcella, G.; Scelba, G.; Rizzo, Mattia A.; Nardo, Domenico; Scollo, Rosario; Scuto, Alfio; Sorrentino, Giuseppe

doi:10.23919/aeitautomotive50086.2020.9307440

Cited by 4 publications

(2 citation statements)

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“…Then, a new technique based on an inductive rather than resistive gate driver impedance was proposed to mitigate or even completely compensate for the effects of source inductance in 3L MOSFET. In [17], the experimental results highlighted that the 4L MOSFET performs better than the 3L one in high currents applications, while the higher cost of the former limits their use in low-current applications. A comparison of the double pulse test switching losses of a 3L and 4L SiC MOSFET has been reported in [27].…”

Section: A Academia and Industry Experiencementioning

confidence: 99%

“…The advantages deriving from the use of a MOSFET equipped with a Kelvin pin (4L MOSFET) in comparison with a 3-lead device (3L MOSFET) increase as the current increases, making the former interesting in high currents applications [17]. More specifically, for both kinds of packages, the switching losses increase with increasing current, but the increment is lower in 4L MOSFETs compared to 3L ones as the current increases.…”

Section: Introductionmentioning

confidence: 99%

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Actual Reasons Involving Turn-Off Losses Improvement With Increasing Load and Gate Resistance in MOSFETs Enhanced With Kelvin Source

Rizzo

2024

IEEE Trans. Ind. Electron.

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This paper explains the actual reasons behind the improvement in terms of turn-off energy losses (Eoff) reduction, obtained using Kelvin pin (4-lead, 4L) MOSFETs instead of 3L ones. Eoff increases by increasing gate resistance and load, but the experimental results reveal that the increment is less in 4L than in 3L MOSFETs. Analysing the turn-off waveforms and adopting circuit analysis, the paper first proves that the common argument about the undesired effect of the parasitic source inductance in 3L MOSFETs is misleading. Then, the reasons behind the aforesaid improvement in 4L MOSFETs with increasing gate resistance and load are described by means of the derived analytical expressions. Finally, the analysis of the equations has provided helpful information at the design stage, also accounting for the different device technologies. In particular, the improvement obtained using 4L MOSFETs reduces as the driving loop parasitic inductance increases and evanesces if its value becomes comparable with the power loop parasitic inductance.

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Section: A Academia and Industry Experiencementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%