Understanding the Kelvin pin mitigation of the MOSFET turn-on losses by fast-switching and neutralization of the clamp diode

Giorgio, Francesco; Rizzo, Santi Agatino; Scarcella, G.; Scuto, Alfio; Sorrentino, Giuseppe

doi:10.1109/iecon48115.2021.9589172

Cited by 1 publication

(4 citation statements)

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“…For example, at full load, the loss difference between 3L and 4L quadruples when passing from RG=3.9 to RG=15. The same effect occurs on the turn-on energy losses, although the reasons are different, as proved by authors in [24].…”

Section: B Experimental Analysis Of 3l and 4l Mosfets Eoff: Impact Of...mentioning

confidence: 59%

“…1b). Similar reasoning is usually adopted to explain the advantages during the turn-on [24]. Indeed, such an interpretation is valid only for the turn-on, not for the turnoff, as we will prove in the following.…”

Section: Introductionmentioning

confidence: 64%

“…However, it is worth noticing that these considerations account for the turn-off only. A proper design must also consider the behavior during the turn-on [24].…”

Section: Discussionmentioning

confidence: 99%

“…The turn-on energy losses measured experimentally for different load conditions in [24] have shown that the energy advantage of the 4L is reduced at low load. This is due to the drain-source voltage waveform of the 3L device, which is more similar to those of the 4L one at a low current.…”

Section: A Academia and Industry Experiencementioning

confidence: 99%

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Actual Reasons Involving Turn-Off Losses Improvement With Increasing Load and Gate Resistance in MOSFETs Enhanced With Kelvin Source

Rizzo

2024

IEEE Trans. Ind. Electron.

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This paper explains the actual reasons behind the improvement in terms of turn-off energy losses (Eoff) reduction, obtained using Kelvin pin (4-lead, 4L) MOSFETs instead of 3L ones. Eoff increases by increasing gate resistance and load, but the experimental results reveal that the increment is less in 4L than in 3L MOSFETs. Analysing the turn-off waveforms and adopting circuit analysis, the paper first proves that the common argument about the undesired effect of the parasitic source inductance in 3L MOSFETs is misleading. Then, the reasons behind the aforesaid improvement in 4L MOSFETs with increasing gate resistance and load are described by means of the derived analytical expressions. Finally, the analysis of the equations has provided helpful information at the design stage, also accounting for the different device technologies. In particular, the improvement obtained using 4L MOSFETs reduces as the driving loop parasitic inductance increases and evanesces if its value becomes comparable with the power loop parasitic inductance.

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Section: B Experimental Analysis Of 3l and 4l Mosfets Eoff: Impact Of...mentioning

confidence: 59%

Section: Introductionmentioning

confidence: 64%

“…However, it is worth noticing that these considerations account for the turn-off only. A proper design must also consider the behavior during the turn-on [24].…”

Section: Discussionmentioning

confidence: 99%

Section: A Academia and Industry Experiencementioning

confidence: 99%

See 2 more Smart Citations