High-energy ion implantation for ULSI

Tsukamoto, K.; Komori, S.; Kuroi, T.; Akasaka, Youichi

doi:10.1016/0168-583x(91)95283-j

Cited by 78 publications

(20 citation statements)

References 8 publications

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“…There are other advantages of the MeV ion implantation technique, e.g., process simplicity, lower thermal budget, chip size reduction, and improved surface topography. [6][7][8] Although there was a report that high-energy ion implantation caused little damage at substrate surfaces due to the predominant electronic stopping power, and thus relatively good crystallinity was retained in the surface and bulk regions, 9) the results of the present work show that the integrity of the thin gate oxide grown on the MeV ionimplanted Si substrate suffered to some extent, and that an appropriate annealing scheme is necessary to prevent degradation.…”

Section: Introductionmentioning

confidence: 82%

Post-Implantation Thermal Annealing Effect on the Gate Oxide of Triple-Well-Structure

Hsu¹,

Liang

Lin

et al. 2002

Jpn. J. Appl. Phys.

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In this work, we investigate the effect of post-implantation thermal annealing on the quality of thin gate oxides grown on MeV ion-implanted Si substrates for the triple-well structure. The thin gate oxide grown on the MeV ion-implanted Si substrates without post-implantation thermal annealing may contain pinholes, leading to oxide failure at a very low voltage; in addition, the gate oxide has a higher density of interface states, which may result in a low breakdown voltage. With appropriate postimplantation thermal annealing before the growth of the gate oxide, e.g., 1000 C for 30 min under the MeV implantation conditions employed in this work, the gate oxide is able to regain its integrity in terms of electrical breakdown voltage.

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Section: Introductionmentioning

confidence: 82%

Post-Implantation Thermal Annealing Effect on the Gate Oxide of Triple-Well-Structure

Hsu¹,

Liang

Lin

et al. 2002

Jpn. J. Appl. Phys.

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“…5 These defects could act as gettering sites, and the benefits associated with these gettering sites are improved device performance and reliability. 6 To Defects in Annealed 1.5 MeV Boron Implanted p-type Silicon J.Y. DAI, 1,4 K.K.…”

Section: Introductionmentioning

confidence: 99%

Defects in annealed 1.5 MeV boron implanted p-type silicon

Ong

Liu

et al. 2001

Journal of Elec Materi

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“…Also, in this paper the simulation results are described for the charge collection, which is induced by incident particles, in n+ layers with a retrograde well structure [9].…”

Section: Introductionmentioning

confidence: 99%

Soft-error study of DRAMs using nuclear microprobe

Ohno

Kimura

Sonoda

et al. 1993

31st Annual Proceedings Reliability Physics 1993

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A new method for evaluation of soft-errors in DRAMs using a nuclear microprobe has been developed in order to investigate the local sensitive structure. The susceptibility in the mapping image of a soft-error caused by ion's incident onto or near a storage cell in DRAM is possible to be directly monitored by this method. Softerrors are induced within 4um around the monitored memory cell. The retrograde well formed by MeV ion implantation has experimentally shown a reduction in soft-errors. The charge collection into n+ layers with a retrograde well and a conventional well was estimated through the device simulation. These simulations coincided with the experimental results.

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High-energy ion implantation for ULSI

Cited by 78 publications

References 8 publications

Post-Implantation Thermal Annealing Effect on the Gate Oxide of Triple-Well-Structure

Post-Implantation Thermal Annealing Effect on the Gate Oxide of Triple-Well-Structure

Defects in annealed 1.5 MeV boron implanted p-type silicon

Soft-error study of DRAMs using nuclear microprobe

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