High efficiency class-F power amplifier integrated with microstrip asymmetric lowpass filter

Hayati, Mohsen; Shama, Farzin

doi:10.1007/s10470-018-1356-5

Cited by 5 publications

(2 citation statements)

References 26 publications

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“…Roff et al [40] involve presenting harmonic impedances externally to the device to terminate all of the harmonics properly. Hayati proposed novel approaches like the use of asymmetric lowpass filter [41] and biasing of harmonic control network with Lowpass Filter (LPF) [42] to realise and suppress harmonics at lower frequencies. For higher frequencies and at the fundamental value, a simple lowpass matching network at the drain output of CMOS PA cancels out the reactive part of the load, while the series parasitic inductance is incorporated into a second harmonic short and the parallel parasitic capacitance resonates with that external short to present a high impedance termination to the third harmonic.…”

Section: (A) (B)mentioning

confidence: 99%

Design and optimisation of high‐efficient class‐F ULP‐PA using envelope tracking supply bias control for long‐range low power wireless local area network IEEE 802.11ah standard using 65 nm CMOS technology

Akhter

Amin

Zia

2022

IET Circuits, Devices & Syst

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This article presents the design and optimisation of a sub‐1 GHz class‐F ultra‐low power (ULP) power amplifier (PA) in 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. An envelope tracking (ET) supply biasing technique is adopted to improve the efficiency of class‐F PA. The ET consist of a pre‐amp right before the detector in order to enhance the efficiency and save adequate amount of dc power consumption. The PA consists of two cascode cells terminated as class‐F with gate‐to‐drain feedback in order to enhance linearity and limit any harmonic component from the input signal. The novel design consumes a dc power of 3.75 mW, power added efficiency of 37.1%, operating at 915–925 MHz unlicensed band and total saturated output power of 22 dBm including 14 dBm power gain at PA, which qualifies under long‐range low power wireless local area network IEEE 802.11ah standard. The inductor‐less design for ET supply bias reduces the chip layout size to 0.13 mm2 only.

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Section: (A) (B)mentioning

confidence: 99%

Design and optimisation of high‐efficient class‐F ULP‐PA using envelope tracking supply bias control for long‐range low power wireless local area network IEEE 802.11ah standard using 65 nm CMOS technology

Akhter

Amin

Zia

2022

IET Circuits, Devices & Syst

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“…Combining class-F PAs and filter structures can achieve high efficiency and broadband simultaneously. Class-F PAs aim to reshape the drain voltage by opening the odd harmonics and shorting the even harmonics so that the drain voltage and current do not overlap and improve its efficiency [25,26,27]. In order to simplify the circuit, only the second and third harmonics are controlled, which limits its bandwidth and efficiency to a certain extent.…”

Section: Introductionmentioning

confidence: 99%

Design of broadband power amplifier based on loop-shaped filter matching structure

Chen

You

Liu

et al. 2023

IEICE Electron. Express

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A method for designing a broadband high-efficiency power amplifier (PA) based on a novel loop-shaped filter matching structure is proposed in this paper. By combining a power amplifier matching circuit and a loop-shaped filter structure, a broadband high-efficiency PA based on a new harmonic matching structure is realized. The novel loop-shaped filter can control the second and third harmonics in a wide frequency range and has a specific control effect on higher-order harmonics, which can further expand the bandwidth of class-F PA and improve efficiency. To verify its feasibility, a power amplifier with a bandwidth of 1.6 GHz-3.4 GHz, a saturated output power greater than 41 dBm, a drain efficiency of 65% -72% with a gain greater than 10dB is designed and fabricated using GaN HEMT CGH40010F transistor.

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High-performance class-E power amplifier integrated with a microstrip bandpass-filter for wireless applications

Afzali

Shama

Abbasi

2021

Analog Integr Circ Sig Process

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High efficiency class-F power amplifier integrated with microstrip asymmetric lowpass filter

Cited by 5 publications

References 26 publications

Design and optimisation of high‐efficient class‐F ULP‐PA using envelope tracking supply bias control for long‐range low power wireless local area network IEEE 802.11ah standard using 65 nm CMOS technology

Design and optimisation of high‐efficient class‐F ULP‐PA using envelope tracking supply bias control for long‐range low power wireless local area network IEEE 802.11ah standard using 65 nm CMOS technology

Design of broadband power amplifier based on loop-shaped filter matching structure

High-performance class-E power amplifier integrated with a microstrip bandpass-filter for wireless applications

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