High density packaging in 2010 and beyond

Tummala, Rao; Liu, Fuhan; White, G. Edward; Hattacharya, S.; Pulugurtha, Raj; Swaminathan, Madhavan; Dalmia, S.; Laskar, J.; Jokerst, N.M.; Chow, Sang Yeon

doi:10.1109/emap.2002.1188809

Cited by 20 publications

(5 citation statements)

References 4 publications

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“…In these geometries, a significant portion of the passive elements are located not on-chip (where possible), but rather on-package thereby saving chip real estate, improving performance, and reducing cost since the package is inevitably cheaper than the corresponding semiconductor material. The demands for compactness and functionality, as well as the close proximity of these passives to the antenna [3], especially for 802.11x/Bluetooth compact modules, make the design and optimization processes of such systems more and more challenging.…”

Section: Introductionmentioning

confidence: 99%

Design and optimization of 3-D compact stripline and microstrip Bluetooth/WLAN balun architectures using the design of experiments technique

Staiculescu

Bushyager

Obatoyinbo

et al. 2005

IEEE Trans. Antennas Propagat.

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Abstract-In this paper, various architectures of 3D compact microwave balanced to unbalanced (balun) transformers for Bluetooth/WiFi antenna applications are successfully designed and optimized using the Design of Experiments (DOE) approach. Two different multilayer topologies, one microstrip and one stripline, are investigated on Low Temperature Co-fired Ceramic (LTCC) substrate. The design goals for both baluns are perfectly balanced outputs from 2 to 3 GHz and a resonant frequency of exactly 2.4 GHz. It is demonstrated, using only eight simulations, that perfectly balanced outputs are not possible under the given conditions in the case of the microstrip balun. Nevertheless, the stripline balun can be optimized due to its almost symmetrical structure, and both simulations and measurement results verify the conclusions. The DOE method is very simple to implement and gives a clear understanding of the system behavior at the beginning of the design process, reducing the amount of work required for achieving the design goals by orders of magnitude compared to the widely used trial-and-error approach. The matching and unique measurement issues regarding the calibration, placement of probes and the deembedding of the microstrip to coplanar waveguide (CPW) transitions are discussed in detail for the optimized stripline balun. This technique can be easily applied to the fast and efficient optimization of complicated radiation structures, such as reconfigurable or multilayer mutliband antenna arrays.

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Section: Introductionmentioning

confidence: 99%

Design and optimization of 3-D compact stripline and microstrip Bluetooth/WLAN balun architectures using the design of experiments technique

Staiculescu

Bushyager

Obatoyinbo

et al. 2005

IEEE Trans. Antennas Propagat.

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“…Wire bond machines utilize precise control of bonding force, ultrasonic vibration, bonding temperature and bonding time to establish the connection between gold wire to bond pad or leadframe. The trend of increased integration has resulted in new challenges for wire bond process; mainly because more wires are bonded on a chip and pad pitch has become smaller [3]. A single semiconductor product can contain as much as 600 wires and pitch distance can be as low as 50 micron or smaller [4].…”

Section: Introductionmentioning

confidence: 99%

Wire Bonding Using Offline Programming Method

Foo¹

2010

Engineering

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Manual process of creating bonding diagram is known to be time consuming and error prone. In comparison, offline programming (OLP) provides a much more viable option to reduce the wire bonding creation time and error. OLP is available in two versions, i.e., vendor specific OLP and direct integration offline programming (Di-OLP). Both versions utilize the bonding diagram and computer aided design data to speed up bonding program creation. However, the newly proposed Di-OLP is more flexible as it can be used to create bonding program for multiple machine platforms in microelectronics industry. Some special features of Di-OLP method are presented. The application of generic OLP however, is applicable to machines that recognize ASCII text file. The user needs to know the data format accepted by machine and convert the data accordingly to suit its application for different machine platforms. Di-OLP is also a practical method to replace the time consuming manual method in production line.

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“…Since the past decades, the demands of fabricating cheaper consumer electronic products having compact size, faster response, better performance and additional functionalities, are growing with each passing day. The continuously increasing demands have motivated the researchers to develop the next generation of electronic products [1][2][3][4][5].…”

Section: Present Status and Future Trends In The Microsystems Packagingmentioning

confidence: 99%

“…These nano-size ICs are expected to carry more than 100 million transistors, which will further require an interconnect density of more than 10,000 I/Os cm -2 , for the 1 st level interconnects (Figure 1.1b). These kind of highly dense 1 st level interconnects will be needed in the advanced next generation of microprocessors where signal lines can have more than 200 I/Os, while the power and ground connections may be in order of 2000 [5]. Such a fine pitch is not possible in the conventional interconnection techniques such as flip chip, wire bonding etc, where the interconnect pitch size is in the range of 200 µm (ultra fine pitch) to 400 µm (fine pitch) and thus, limits the density of I/Os to 625-2500 cm -2 .…”

Section: Reduced Package Size and Higher Density Of I/o's Per Chipmentioning

confidence: 99%

“…As described earlier, present chip-to-package interconnects have several serious issues like longer interconnection length, higher RC delay, larger footprint area on PCB bonding pad, and smaller I/Os density, etc [3][4][5][6]59]. Due to these restraints of the conventional interconnections, the efforts are focused on the development of alternate interconnect technology.…”

Section: Motivationmentioning

confidence: 99%

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Fabrication & characterization of high aspect ratio fine pitch deep reactive ion etched through-wafer electroplated copper interconnects

Dixit¹

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, for providing their full support. • To my childhood friends Waseem Ahmed, Manish Tiwari, Alok Yadav, Goverdhan Dobhal, my brother Sandeep Dixit and sister Shalini Dixit and many others for their friendly support and advice. Finally my special gratitude is towards my parents and family, for their love, encouragement and support throughout my research duration. Without my parents, I would not have learnt the meaning of working hard. By creating the opportunities for me to have a good education, they have provided me the best possible thing, I could have ever wished for. To them, I am eternally grateful. Special thanks and appreciation are to my girl friend Zhao Jin, for standing besides me during the tough time. Her encouragement and selfless support has motivated me to achieve success in completing this research work. I would also like to thank her parents Liu Huamin and Zhao Anmin for their continuous trust and support.

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High density packaging in 2010 and beyond

Cited by 20 publications

References 4 publications

Design and optimization of 3-D compact stripline and microstrip Bluetooth/WLAN balun architectures using the design of experiments technique

Design and optimization of 3-D compact stripline and microstrip Bluetooth/WLAN balun architectures using the design of experiments technique

Wire Bonding Using Offline Programming Method

Fabrication & characterization of high aspect ratio fine pitch deep reactive ion etched through-wafer electroplated copper interconnects

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