High density packaging for mobile terminals

Pienimaa, S.; Martin, N.

doi:10.1109/ectc.2001.927966

Cited by 7 publications

(3 citation statements)

References 3 publications

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“…There is also a continuing demand for the miniaturization of this module [1]. The 3D integration and stacking of components are also methods that are applied to achieve the miniaturization of systems.…”

Section: Introductionmentioning

confidence: 99%

Electrical Characterization and Design Optimization of Embedded Chip in Substrate Cavities

Sankaran

Lee

Engin

et al. 2007

2007 Proceedings 57th Electronic Components and Technology Conference

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Endless demands for digital convergence by ultraminiaturization, increased functionality, better performance and low cost in both mobile and desktop systems are driving the needs for new and unique solutions in system integration. The requirements of future electronic systems include faster, smaller, lighter and thinner products. Advanced electronic packaging caters to these ultra-miniaturization and performance needs. The approach of embedding passive components has been in the fray for a while now and the relatively newer perspective to sustain the miniaturization trend efficiently is by embedded active chips as well. This paper discusses the electrical design aspects of embedded actives dealing with the chip-last methodology of embedding dies in particular. The various issues that are expected to surface are made clear through electromagnetic simulations using 3D solver tools. The transmission lines forming the substrate wiring when the cavities are made are analyzed comprehensively. A test vehicle is fabricated based on this new approach and preliminary measurement results are also included in this paper.

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Section: Introductionmentioning

confidence: 99%

Electrical Characterization and Design Optimization of Embedded Chip in Substrate Cavities

Sankaran

Lee

Engin

et al. 2007

2007 Proceedings 57th Electronic Components and Technology Conference

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“…Passives, discretes, connectors, and shields occupy the rest of the board. Passive integration, modularization, and stacking enable higher packaging efficiency [2].…”

Section: Introductionmentioning

confidence: 99%

Stacked Modular Package

Pienimaa

Miettinen

Ristolainen

2004

IEEE Trans. Adv. Packag.

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This paper reports on a vertical package developed to enable size reduction of electronics for miniaturized products. The features of portable and handheld devices have increased whereas size is continually reduced. System-on-a-chip is the most effective size reduction approach, but is not a good business when excessively complex and oversized low yielding chips are required. A vertical package is a cost-effective solution to save placement and routing area on the board. Furthermore, a vertical module enables the benefit of several IC processes in the same module. The goal was to develop a method to produce a stacked modular package on a small scale, and to verify the feasibility of the solution. The main focus has been to test the bare die connections to the interposer and the vertical connections between interposers. The structure enables also, e.g., thin discretes, and passive arrays to be assembled on the interposer, thus enabling system-in-package (SiP) solutions. The method has been tested using thin daisy chain dice and daisy chain vertical interconnections. The dimensions of the developed six chip modules were 14 8 0.8 1 mm. This module consists of three aramid-epoxy interposers, each containing two chips. The interposers were either 100 or 150-m thick, and the chips were thinned down to 90 s. Eutectic tin-lead solder bumps were used to mount the flip chips to the interposer. Solder-coated polymer spheres were used to stack the interposers on top of each other. The developed stacking process and vertical area interconnections by plastic core balls give good reliability and uniform stand-off height.Thermal cycling test +125 40 C until 2000 cycles proved reliability of the structure. Flip-chip failures were found after 500 cycles and only 1 of 32 vertical connection failures occurred during the test. Furthermore, this was caused, at least partly, by excess solder. Plastic ball as interconnection media between stacked layers gives good reliability and uniform stand-off height.Index Terms-Miniaturization, solder-coated plastic ball, system-in-package, vertical interconnection, vertical packaging.

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“…As an example, packaging of RF silicon ICs with simultaneous integration of high-quality passives, antennas or isolation structures [1] or protection of MEMS structures [2] can be mentioned. The emerging WLCSP technology and related integrated passive devices (IPDs) have proven to have capabilities of significant size reduction at a comparable cost and an improved electrical performance [3], [4].…”

Section: Introductionmentioning

confidence: 99%

Influence of via-connections on electrical performance of vertically-spaced RF passives

Bartek

Sinaga

Burghartz

Proceedings Electronic Components and Technology, 2005. ECTC '05.

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Electrical performance of via-connected rectangular spiral inductors integrated on a low-loss spacer substrate and thus vertically-spaced above a lossy silicon substrate is analyzed using 3D electromagnetic simulation tool Ansoft HFSS with a goal to identify the optimum via-interconnect scheme. The results show that vertically spaced spiral inductors with a properly designed via-interconnect scheme is a viable option to achieve high-quality passives and to minimize chip area of silicon RF ICs. Improperly designed electrical via interconnect can severely degrade electrical performance of spiral inductors due to the in-via induced eddy currents and/or parasitic capacitances. Smaller via diameters and their larger separations are preferable to minimize parasitic capacitances. The optimum via length (i.e. spacer substrate thickness) is in the range of 100-200 µm, when the influences of a lossy silicon substrate and via capacitances are minimized. IntroductionAs the demand for ever-smaller electronic systems grows, manufacturers are seeking ways to increase IC integration levels and to reduce the size and weight of IC packages. The explosive expansion of mobile electronic terminals generates strong demand for high-performance, cost-effective and miniaturized RF modules providing desired wireless connectivity. Ideally, they should be realized as a single-chip solution and could easily be embedded into any electronic system. Such System-on-Chip (SoC) RF ICs have set a challenge for packaging, especially at the low-end market segment where low-cost solutions are required. The chip size package (CSP) and wafer-level packaging (WLP) resulting from this effort, have been introduced into manufacturing at an unprecedented rate.The driving force behind is not only the reduced size and weight, but primarily the fact that the wafer-level chip-scale packaging (WLCSP) technology has potential of electrical performance improvement at a comparable or even reduced manufacturing cost and thus providing an improved performance-to-price ratio. Moreover, the same processing steps that are used to achieve the WLP technology basic packaging goal can be adopted for implementation of an additional functionality at no or very limited additional cost. As an example, packaging of RF silicon ICs with simultaneous integration of high-quality passives, antennas or isolation structures [1] or protection of MEMS structures [2] can be mentioned. The emerging WLCSP technology and related integrated passive devices (IPDs) have proven to have capabilities of significant size reduction at a comparable cost and an improved electrical performance [3], [4].

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High density packaging for mobile terminals

Cited by 7 publications

References 3 publications

Electrical Characterization and Design Optimization of Embedded Chip in Substrate Cavities

Electrical Characterization and Design Optimization of Embedded Chip in Substrate Cavities

Stacked Modular Package

Influence of via-connections on electrical performance of vertically-spaced RF passives

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