Electrical Characterization and Design Optimization of Embedded Chip in Substrate Cavities

Abstract

Endless demands for digital convergence by ultraminiaturization, increased functionality, better performance and low cost in both mobile and desktop systems are driving the needs for new and unique solutions in system integration. The requirements of future electronic systems include faster, smaller, lighter and thinner products. Advanced electronic packaging caters to these ultra-miniaturization and performance needs. The approach of embedding passive components has been in the fray for a while now and the relatively newer perspective to sustain the miniaturization trend efficiently is by embedded active chips as well. This paper discusses the electrical design aspects of embedded actives dealing with the chip-last methodology of embedding dies in particular. The various issues that are expected to surface are made clear through electromagnetic simulations using 3D solver tools. The transmission lines forming the substrate wiring when the cavities are made are analyzed comprehensively. A test vehicle is fabricated based on this new approach and preliminary measurement results are also included in this paper.

Propagation Behavior of Multilayer Microstrips Applied to Interconnects Running Near Embedded Integrated Components

“…Little research into the high-frequency characteristics of embedded components has been performed, due to the relatively new technology and the atypical geometries that are involved. Research efforts mainly focus on the influence of the facedown embedding cavities on board interconnects [5], [6] or often concentrate on wafer-level packaging [7], [8]. Palm et al [9], Richter et al [10], and Ohshima et al [11] compare measurements of prototype samples to simulations, but do not propose any circuit models.…”