High-Capacity FPGA Router for Satellite Backbone Network

Jankovic, Strahinja; Smiljanic, Aleksandra; Vesovic, Mihailo; Redzovic, Hasan; Bezulj, Marija P.; Radošević, Andreja; Moro, S.

doi:10.1109/taes.2019.2951187

Cited by 11 publications

(3 citation statements)

References 27 publications

(28 reference statements)

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“…Our proposed design can deliver critical flows with PDV values below 1 µs. Furthermore, given the flexibility of the platform, this figure could be further improved in future projects with more relaxed constraints in terms of resources by implementing larger buffers, faster packet processing stages, or more efficient switching interconnects, like the FPGA router design in [64].…”

Section: Discussionmentioning

confidence: 99%

Implementation of a Time-Sensitive Networking (TSN) Ethernet Bus for Microlaunchers

Sanchez-Garrido

Aparicio

Ramírez

et al. 2021

IEEE Trans. Aerosp. Electron. Syst.

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The design of the aerospace systems for future aircraft requires the identification of new, suitable communication infrastructures that can overcome the limitations that often come with the use of the legacy, albeit well-proven, protocols that are routinely integrated in aerospace. This allows us to overcome the bandwidth constraints, large deployment costs or the lack in flexibility of other alternatives, like Spacewire, or legacy systems such as the MIL-STD-1553B bus. These protocols can be replaced with new technologies that can fulfill the greater real-time and interconnectivity demands of advanced scientific probes or manned spacecraft. The advent of the new microlauncher systems has all but confirmed this trend. In this context, we describe the design and implementation of a time-sensitive networking (TSN) bus for the avionics of the Miura 1 suborbital microlauncher. TSN represents an appropriate interface for this type of platform given its ability to provide the determinism and reliability expected in space-grade systems in combination with the higher data rates (Gigabit Ethernet) and greater flexibility of standard Ethernet. This has resulted in a TSN platform developed by Seven Solutions S.L. based on the commercially available Zynq-7000 devices from Xilinx. Thus, our design features a light-footprint field-programmable gate array (FPGA) architecture powered by a real-time executive for multiprocessor systems (RTEMS) operating system, which is currently pending its certification from the European Space Agency (ESA) for space applications. All these elements have been successfully integrated and validated for the avionics of the Miura 1 sounding rocket, which represents an illustrative case that verifies their applicability to similar scenarios.

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Section: Discussionmentioning

confidence: 99%

Implementation of a Time-Sensitive Networking (TSN) Ethernet Bus for Microlaunchers

Sanchez-Garrido

Aparicio

Ramírez

et al. 2021

IEEE Trans. Aerosp. Electron. Syst.

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“…They tested sending video signal packets from the camera to a display with two FPGAs, one for transmission and another for reception. Other research by Janković designed a system architecture on the FPGA for a space router in a satellite that could support a high bit rate of up to 100 Gbps [ 27 ]. This scenario showed an extreme operating condition in space where it was impossible to change the hardware mid-operation, and FPGAs could be an ideal platform for high throughput and flexibility.…”

Section: Related Workmentioning

confidence: 99%

Cost-Effective Network Reordering Using FPGA

Hoang

Chen

2023

Sensors

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The advancement of complex Internet of Things (IoT) devices in recent years has deepened their dependency on network connectivity, demanding low latency and high throughput. At the same time, expanding operating conditions for these devices have brought challenges that limit the design constraints and accessibility for future hardware or software upgrades. These limitations can result in data loss because of out-of-order packets if the design specification cannot keep up with network demands. In addition, existing network reordering solutions become less applicable due to the drastic changes in the type of network endpoints, as IoT devices typically have less memory and are likely to be power-constrained. One approach to address this problem is reordering packets using reconfigurable hardware to ease computation in other functions. Field Programmable Gate Array (FPGA) devices are ideal candidates for hardware implementations at the network endpoints due to their high performance and flexibility. Moreover, previous research on packet reordering using FPGAs has serious design flaws that can lead to unnecessary packet dropping due to blocking in memory. This research proposes a scalable hardware-focused method for packet reordering that can overcome the flaws from previous work while maintaining minimal resource usage and low time complexity. The design utilizes a pipelined approach to perform sorting in parallel and completes the operation within two clock cycles. FPGA resources are optimized using a two-layer memory management system that consumes minimal on-chip memory and registers. Furthermore, the design is scalable to support multi-flow applications with shared memories in a single FPGA chip.

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“…To accurately gauge the performance of our proposed solution, we have implemented the SATNET-OSPF routing protocol on a space router that is prepared for flight. This space router utilizes a two-layer architecture, composed of CPU and FPGA, 43,44 and is capable of managing 2 bidirectional Ground Station Links (GSLs) and 4 bi-directional ISLs. The architecture of this space router is illustrated in Figure 11.…”

Section: Space Router Implementationmentioning

confidence: 99%

Routing in future space‐terrestrial integrated networks with SATNET‐OSPF

Yan,

Qiao,

et al. 2023

Satell Commun Network

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SummaryConnectivity in satellite networks is governed by the spacecraft nodes' orbital dynamics together with the planet's continuous rotation where ground nodes are located. The resulting time‐dynamic but predictable topology demands the design of specific distributed routing schemes. However, terrestrial Internet routing schemes' maturity, proven scalability, and efficiency shall be leveraged whenever possible to facilitate space‐terrestrial integration while reducing risk and costs. In line with this reflection, we introduce SATNET‐OSPF: a backward‐compatible satellite extension for the widely used Open Shortest Path First routing protocol. The key features of SATNET‐OSPF are (a) accurate routing interface mapping to inter‐satellite links and ground‐to‐satellite links, (b) accelerated link‐up/link‐down event detection adapted to space‐specific wireless technologies, (c) proactive routing and forwarding mechanism to take advantage of predicted link‐down events, and (d) low memory footprint topology model to efficiently propagate the forthcoming space connectivity events via constrained telecommand links. Leveraging existing IPv6 and OSPFv3 open‐source stacks, we implemented SATNET‐OSPF in an actual space router comprising a space‐grade SPARC V8 CPU and a radiation‐hardened FPGA. Furthermore, we present the details of an emulation test bench supporting various configurations with COTS terrestrial OSPF routers that enabled a realistic performance evaluation of the SATNET‐OSPF. Results show that SATNET‐OSPF reduced OSPFv3 routing protocol overhead by up to 31%; shortened the link event detection delay by four orders of magnitude; decreased the routing outage by a factor of 22; and ensured flooding control message generation and forwarding times, as well as routing computing time, satisfy the original requirements (192, 37, and 17 ms, respectively).

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High-Capacity FPGA Router for Satellite Backbone Network

Cited by 11 publications

References 27 publications

Implementation of a Time-Sensitive Networking (TSN) Ethernet Bus for Microlaunchers

Implementation of a Time-Sensitive Networking (TSN) Ethernet Bus for Microlaunchers

Cost-Effective Network Reordering Using FPGA

Routing in future space‐terrestrial integrated networks with SATNET‐OSPF

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