Modern networks used for integrating custom Internet of Things (IoT) systems and devices have restrictions and requirements unique to their individual applications. These application specific demands require custom designed hardware to maximize throughput, security and data integrity whilst minimizing latency, power consumption, and form factor. Within this paper, we describe current, state-of-the-art works that utilize FPGAs for IoT network developments. We analyze two categories of works: those that prioritize reducing power consumption, and those that prioritize networking features. Further, we describe how future works can improve upon these designs and therefore improve the efficiency of resource-constrained IoT networks.
Smart cars have gained much attention in recent years due to the introduction of several safety and convenience features. In this paper, we propose a virtual CANBUS architecture that will improve the safety and data processing in future smart cars with the hybrid use of Ethernet technology deployed in conjunction with a CANBUS system to take advantage of the virtualization, speed, and quality of data processing. Data will be routed intelligently across the dual data paths of the traditional CANBUS and the Ethernet. The virtualized nature, with the help of a series of smart nodes and network traffic analyzers, will allocate the needed resources at the right time during the execution of different processes. This enables the possibility of routing data traffic over both Ethernet and CANBUS connections. The architecture is backward compatible with older vehicles and therefore takes advantage of the existing CANBUS system. The proposed architecture ensures that different segments are isolated from each other so that a breakdown in a segment does not bring down the entire system. The experimental results demonstrate the benefits of the proposed solution, which is to switch between two data pathways depending on the traffic loads. While the CANBUS is sufficient with low-bandwidth data, the Ethernet will create a better performance with high-bandwidth processes. The virtualized environment creates virtual topologies among communicating nodes, greatly simplifying the network management and enhancing the data traffic performance as the bandwidth requirement and the number of processors in future smart cars continue to scale.
The advancement of complex Internet of Things (IoT) devices in recent years has deepened their dependency on network connectivity, demanding low latency and high throughput. At the same time, expanding operating conditions for these devices have brought challenges that limit the design constraints and accessibility for future hardware or software upgrades. These limitations can result in data loss because of out-of-order packets if the design specification cannot keep up with network demands. In addition, existing network reordering solutions become less applicable due to the drastic changes in the type of network endpoints, as IoT devices typically have less memory and are likely to be power-constrained. One approach to address this problem is reordering packets using reconfigurable hardware to ease computation in other functions. Field Programmable Gate Array (FPGA) devices are ideal candidates for hardware implementations at the network endpoints due to their high performance and flexibility. Moreover, previous research on packet reordering using FPGAs has serious design flaws that can lead to unnecessary packet dropping due to blocking in memory. This research proposes a scalable hardware-focused method for packet reordering that can overcome the flaws from previous work while maintaining minimal resource usage and low time complexity. The design utilizes a pipelined approach to perform sorting in parallel and completes the operation within two clock cycles. FPGA resources are optimized using a two-layer memory management system that consumes minimal on-chip memory and registers. Furthermore, the design is scalable to support multi-flow applications with shared memories in a single FPGA chip.
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