High capacity and automatic functional extraction tool for industrial VLSI circuit designs

Abstract

In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV-Extract and is part of a comprehensive Formal Equivalence Verification (FEV) system developed at Intel to verify modern microprocessor designs. FEV-Extract employs a powerful hierarchical analysis procedure, and advanced and generic algorithms for automatic recognition of logical primitives, to cope with variety of circuit design styles and their complexity. Logic equations are then extracted to generate a behavioral RTL model described in industrial standard HDL languages, to be used in the formal equivalence verification, logic simulation, synthesis and testability flows.

Verifying equivalence of memories using a first order logic theorem prover

“…There are several variations: write/read via a certain port might be possible to/from an entire row or only parts of it (say to the MSB half or the LSB half). A previous work on identifying memory cells, in Intel's schematic extraction tool, is reported in [21]. The memory identification capability that was developed there enabled an improved modeling of latches that serve as memory cells in special types of memories.…”

“…That work does not support the abstraction of a collection of latches into memories, or the identification of decoders. Our work builds on [21]. To enable equivalence checking of RTL and schematic memories at a higher level of abstraction, we have developed a capability for identifying the memory arrays and the address decoders in memory units.…”

“…In the past, it was impossible to apply advanced term-level verification algorithms to the equivalence checking of RTL and schematic models since the schematics extraction tools [7], [21] could identify logic and state elements (e.g., latches) in the circuit but could not identify memory arrays, decoders, and bit-vector operations.…”

A highly efficient method for extracting FSMs from flattened gate-level netlist

“…As part of the design flow, specifically for formal verification [1] and for high-level design-for-testability (DFT) [2], it is imperative that modern CAD tools are able to comprehensively extract highlevel modules (of a circuit) from its low level description. In other IC-design related processes/issues, transforming a detailed design description into successively higher levels of abstraction is also used in copyright infringement investigation and competitive analysis [3].…”

Transistor Level Timing Analysis Considering Multiple Inputs Simultaneous Switching

“…Gate extraction of transistor circuits has been studied for nearly twenty years. Verity [5],SLV [4], and FEV-Extract [9] have been used in the verification of commercial microprocessors. The main problem still lies in gate delay calculation.…”