A highly efficient method for extracting FSMs from flattened gate-level netlist

Shi, Yong; Ting, Chan Wai; Gwee, Bah-Hwee; Ren, Yi

doi:10.1109/iscas.2010.5537093

Cited by 57 publications

(29 citation statements)

References 4 publications

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“…While any sequential circuit can be trivially viewed as a monolithic FSM, the challenge is to be able to decompose that FSM into a set of smaller FSMs, each of which performs a distinguishable function, thus making the resulting high-level description easier for a human to understand. The recent work by Shi et al [33] is a step in this direction.…”

Section: Related Workmentioning

confidence: 95%

Formal Methods for Reverse Engineering Gate-Level Netlists

Li¹

2013

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Section: Related Workmentioning

confidence: 95%

Formal Methods for Reverse Engineering Gate-Level Netlists

Li¹

2013

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“…While any sequential circuit can be trivially viewed as a monolithic FSM, the challenge is to be able to decompose that FSM into a set of smaller FSMs, each of which performs a distinguishable function, thus making the resulting highlevel description easier for a human to understand. The recent work by Shi et al [20] is a step in this direction. A key component of our work is to find the input-output signal correspondence between an abstract component and a block in the unknown circuit.…”

Section: Related Workmentioning

confidence: 95%

Reverse engineering circuits using behavioral pattern mining

Wasson

Seshia

2012

2012 IEEE International Symposium on Hardware-Oriented Security and Trust

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Systems are increasingly being constructed from off-the-shelf components acquired through a globally distributed, untrusted supply chain. The lack of trust in these components necessitates additional validation of the components before use. Additionally, hardware trojans are becoming a pressing concern. In this paper, we present a novel formalism and method to systematically derive the highlevel function of an unknown circuit component given its gate-level netlist. We define the high-level description of a circuit as an interconnection of instantiations of abstract library components characterized using logical specifications. The proposed approach is based on mining interesting behavioral patterns from the simulation traces of a gate-level netlist, and representing them as a pattern graph. A similar pattern graph is also generated for library components. Our method first computes input-output signal correspondences via subgraph isomorphism on the pattern graphs. The general function of the unknown circuit is then determined by finding the closest match in the component library, by model checking the unknown circuit against each logical specification. We demonstrate the effectiveness of our approach on publicly-available circuits.

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“…In a case study, Hansen et al [22] described several best-practices for a human analysts to reverse engineer gate-level netlists. Shi et al [23] evaluated a technique to automatically reverse engineer circuitry that control units, i.e. Finite State Machine (FSM) from gatelevel netlists.…”

Section: Gate-level Netlist Reverse Engineeringmentioning

confidence: 99%

Hardware reverse engineering: Overview and open challenges

Fyrbiak

Strauß

Kison

et al. 2017

2017 IEEE 2nd International Verification and Security Workshop (IVSW)

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Hardware reverse engineering is a universal tool for both legitimate and illegitimate purposes. On the one hand, it supports confirmation of IP infringement and detection of circuit malicious manipulations, on the other hand it provides adversaries with crucial information to plagiarize designs, infringe on IP, or implant hardware Trojans into a target circuit. Although reverse engineering is commonplace in practice, the quantification of its complexity is an unsolved problem to date since both technical and human factors have to be accounted for. A sophisticated understanding of this complexity is crucial in order to provide a reasonable threat estimation and to develop sound countermeasures, i.e. obfuscation transformations of the target circuit, to mitigate risks for the modern IC landscape.The contribution of our work is threefold: first, we systematically study the current research branches related to hardware reverse engineering ranging from decapsulation to gate-level netlist analysis. Based on our overview, we formulate several open research questions to scientifically quantify reverse engineering, including technical and human factors. Second, we survey research on problem solving and on the acquisition of expertise and discuss its potential to quantify human factors in reverse engineering. Third, we propose novel directions for future interdisciplinary research encompassing both technical and psychological perspectives that hold the promise to holistically capture the complexity of hardware reverse engineering.

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A highly efficient method for extracting FSMs from flattened gate-level netlist

Cited by 57 publications

References 4 publications

Formal Methods for Reverse Engineering Gate-Level Netlists

Formal Methods for Reverse Engineering Gate-Level Netlists

Reverse engineering circuits using behavioral pattern mining

Hardware reverse engineering: Overview and open challenges

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