High accurate pattern based precondition method for extremely large power/ground grid analysis

Shi, Jin; Cai, Yici; Tan, Sheldon X.-D.; Hong, Xianlong

doi:10.1145/1123008.1123029

Cited by 4 publications

(1 citation statement)

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“…The most significant advantage of this simplification is that the power grid problem mathematically reduces to solving a linear system of equations. Thus we can apply techniques from numerical linear algebra to solve the linear system of equations arising from the power grid [2][3][4][5][6][7][8][9]. Hierarchical analysis has also been used to analyze power grid [10,11].…”

Section: Introductionmentioning

confidence: 99%

Accurate power grid analysis with behavioral transistor network modeling

Ramalingam

Devarayanadurg

Pan

2007

Proceedings of the 2007 International Symposium on Physical Design

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In this paper, we propose fast and efficient techniques to analyze the power grid with accurate modeling of the transistor network. The solution techniques currently available for power grid analysis rely on a model of representing the transistor network as a current source. The disadvantage of the above model is that the drain capacitance of the PMOS transistors which are already on is not modeled. The drain capacitance of the PMOS transistors which are on, act much like a decoupling capacitance in the power grid. By ignoring the drain capacitance, the voltage drop predicted is pessimistic. This implies that a designer is likely to overestimate the amount of decoupling capacitance needed. In our proposed model, we model the transistor network as a simple switch in series with a RC circuit. The presence of switches leads to a non-constant conductance matrix. So, the switch is modeled behaviorally to make the conductance matrix a constant in presence of switches. The resulting conductance matrix is a M-matrix thus making it amenable to linear algebraic methods presented in the literature. The proposed model is nearly as accurate as the SPICE model in predicting the voltage drop. We demonstrate that the current source model of the transistor network has an error of about 10% in predicting the voltage drop. The proposed model offers the middle ground between the accuracy of SPICE simulation and the speed of the current source model. The proposed model is 20 − 30× faster than SPICE. It also reduces the size of the decoupling capacitance by 2 − 10× in comparison with the methods presented in the literature.

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