Hierarchical Request-Size-Aware Flash Translation Layer Based on Page-Level Mapping

Abstract

Owing to the increasing Internet population, there has been an explosion in the amount of digital data generated and also an increase in data complexity. This trend is called big data paradigm. As the Internet of Things (IoT) takes center stage, the growth of data will continue to increase. Therefore, the demand for mass storage devices that have high access speed is increasing. Industry has been paying attention to flash memories that can process large amounts of data at high speed. It will be a good alternative for storing and processing ever-increasing amounts of data because of low power consumption, high shock resistance, portability and fast access speed. However, the write speed is about 10–20 times slower than the read speed in flash memory. In addition, write operations are not allowed to be performed with in-place updates. Garbage collection mechanism is proposed in order to solve the problem incurred by the not-in-place update property of write operations. However, garbage collection mechanism unavoidably causes overhead of additional internal operations, which leads to performance degradation. In this paper, to prevent performance degradation caused by garbage collection, we propose a request-size-aware flash translation layer (RSaFTL) and a hierarchical request-size-aware flash translation layer (HiRSaFTL). They are designed based on page-level address translation. In RSaFTL and HiRSaFTL, page-sized data with high temporal locality cluster into a special area called active blocks by exploiting the property of realistic traces. As a result of the experiments, RSaFTL and HiRSaFTL reduce the number of pages migrated during garbage collections by up to 17.9% and 21.3%, respectively, compared with pure page-level flash transition layer.