Hierarchical power management for asymmetric multi-core in dark silicon era

Muthukaruppan, Thannirmalai Somu; Pricopi, Mihai; Venkataramani, Vanchinathan; Mitra, Tulika; Vishin, Sanjay

doi:10.1145/2463209.2488949

Cited by 157 publications

(96 citation statements)

References 14 publications

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“…We here briefly introduce the architecture of the framework presented in [22], on top of which our proposal is built. The original solution manages energy consumption at the node level, where the node has an ARM big.LITTLE architecture, integrating two high performing, complex, out-of-order ARM Cortex-A15 and three energy-efficient, simple, in-order ARM Cortex-A7 cores on the same chip.…”

Section: State Of Art Frameworkmentioning

confidence: 99%

“…Second, the overhead of invoking the age balancer is high if compared to the one of DVFS controller. In ARM big.LITTLE, the overhead of migrating application across clusters is in the order of milliseconds (from 2 to 4 ms) [22]. Therefore, the age balancer has to be invoked very infrequently.…”

Section: A Single Node Scenariomentioning

confidence: 99%

“…Therefore, the age balancer has to be invoked very infrequently. Lastly, the overhead of changing voltage-frequency levels is quite minimal [22]. Changing voltage-frequency levels can positive impact the energy consumption of the system; therefore, the DVFS controller is invoked at a higher frequency.…”

Section: A Single Node Scenariomentioning

confidence: 99%

“…This flexibility introduces many possibilities as well as new challenges and issues, including an increased complexity for application mapping and resource management, to be optimized at runtime to adapt to the working conditions that may not necessarily be known in advance. Asymmetric architectures have already been proven to be beneficial in improving performance and power/energy consumption [22]. However, if the adopted policies do not take into account how they affect the system lifetime, the architecture reliability might be significantly affected.…”

Section: Introduction and Related Workmentioning

confidence: 99%

“…This work proposes a resource management framework designed as an evolution of the solution presented in [22], which is focused on a power management technique for asymmetric multicores that can provide satisfactory user experience while minimizing energy consumption. We aim at building our lifetime optimization framework on the top of it, to make it aware of the components aging and exploit resource management so to extend the overall system lifetime without negatively impacting energy consumption.…”

Section: Introduction and Related Workmentioning

confidence: 99%

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Combined on-line lifetime-energy optimization for asymmetric multicores

Bolchini

Carminati

Mitra

et al. 2016

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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Abstract-In this paper we present an architectural and online resource management solution to optimize lifetime reliability of asymmetric multicores while minimizing the system energy consumption, targeting both single nodes (multicores) as well as multiple ones (cluster of multicores). The solution exploits the different characteristics of the computing resources to achieve the desired performance while optimizing the lifetime/energy tradeoff. The experimental results show that a combined optimization of energy and lifetime allows for achieving an extended lifetime (similar to the one pursued by lifetime-only optimization solutions) with a marginal energy consumption detriment (less than 2%) with respect to energy-aware but aging-unaware systems.

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Section: State Of Art Frameworkmentioning

confidence: 99%

Section: A Single Node Scenariomentioning

confidence: 99%

Section: A Single Node Scenariomentioning

confidence: 99%

Section: Introduction and Related Workmentioning

confidence: 99%

Section: Introduction and Related Workmentioning

confidence: 99%

See 3 more Smart Citations

Combined on-line lifetime-energy optimization for asymmetric multicores

Bolchini

Carminati

Mitra

et al. 2016

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

Self Cite

View full text Add to dashboard Cite

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On power capping and performance optimization of multithreaded applications

Conoci

Sanzo

Pellegrini

et al. 2021

Concurrency and Computation

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Summary Multithreaded applications facilitate the exploitation of the computing power of multicore architectures. On the other hand, these applications can become extremely energy‐intensive, in contrast with the need for limiting the energy usage of computing systems. In this article, we explore the design of techniques enabling multithreaded applications to maximize their performance under a power cap. We consider two control parameters: the number of cores used by the application, and the core power state. We target the design of an autotuning power‐capping technique with minimal intrusiveness and high portability, which is agnostic about the workload profile of the application. We investigate two different approaches for building the strategy for selecting the best configuration of the parameters under control, namely a heuristic approach and a model‐based approach. Through an extensive experimental study, we evaluate the effectiveness of the proposed technique considering two different selection strategies, and we compare them with existing solutions.

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