Hierarchical DFT with enhancements for AC scan, test scheduling and on-chip compression - a case study

Hierarchical DFT with Combinational Scan Compression, Partition Chain and RPCT

“…It is performed by analyzing the interaction between the partitions based on the fact that additional test modes were introduced to increase the coverage. The work presented in [5] was enhanced in [16] by including the ac test, sequential compression technique, and test scheduling techniques. However this done by adding extra logic in the functional path.…”

“…However this done by adding extra logic in the functional path. In addition the sequential compression technique used in [16] increases the area overhead and the complexity of the test architecture. Similar work presented in [17], proposes an algorithm for the isolation technique, in which it utilizes the existing registers, around the I/Os of the block, to create the test collar.…”

“…One of the important challenges in complex SoC testing has been accurate description and realization of system level architecture design of chip. Two most commonly observed Design for Test (DFT) strategies are modular and hierarchical methodologies [1] [2] [3] [5] and [16]. Both the ideas were manifested by understanding the plug-n-play nature of the Intellectual Property (IP) cores, which highlights the heterogeneity in the level of integration and also functional role of each IP block play in a SoC design.…”

“…Fig.1 shows modular scan architecture with wrapper and scan compression. With SoC, designs are becoming more hierarchically organized, there have been some attempts to develop hierarchical DFT [4] [5] [16]. An interesting feature of the hierarchical DFT is that it efficiently makes use of the natural partition of the system architecture and follows the same system level integration flow as that of a modular test procedure.…”

Test cost reduction for the AMD™ Athlon processor using test partitioning

“…Moreover, the routing congestion is lower in the hierarchical approach since the scan chains have to be routed to a local decompressor and compactor instead of a global decompressor and compactor at the top-level. In [24] and [25], the hierarchical compression approach is described in detail and case studies have been shown for large ASIC SOCs. With test partitioning in the CPU core, the hierarchical compression approach can be easily used in the originally non-modular design.…”